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ILI6480G single chip for 480rgbx272 tft panel 720x544 driver with timing controller datasheet preliminary version: v0.04 document no.: ili6480b_ds_v0.04.pdf ili technology corp. 8f, no.38, taiyuan st., jhubei city, hsinchu county 302, taiwan, r.o.c tel.886-3-5600099; fax.886-3-5600055 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 2 of 60 table of contents section page 1. introduction................................................................................................................... ................................. 3 2. features ....................................................................................................................... ................................. 3 3. block diagram .................................................................................................................. ............................. 4 4. applicatio n block.............................................................................................................. ............................. 5 5. charge pump ci rcuit block ...................................................................................................... ..................... 6 6. pin descr iptions ............................................................................................................... ............................. 7 7. 3-wire serial interface ........................................................................................................ ......................... 11 8. register list .................................................................................................................. .............................. 12 9. power on/off sequen ce .......................................................................................................... ................... 32 9.1. power on sequence .............................................................................................................. ........ 32 9.2. power off sequen ce ............................................................................................................. ......... 33 9.3. charge-pump circ uit connection................................................................................................. .. 34 10. input data and output voltage.................................................................................................. .................. 35 11. wire resistance for each pin................................................................................................... ..................... 39 12. dc characte ristic .............................................................................................................. .......................... 40 12.1. absolute maxi mum rating ........................................................................................................ ..... 40 12.2. dc electrical characteristics.................................................................................................. ........ 41 13. ac characteristic .............................................................................................................. .......................... 42 13.1. input signal c haracteristics................................................................................................... .......... 42 14. waveform ....................................................................................................................... ............................. 43 14.1. timing chart................................................................................................................... ................ 43 14.1.1. clock and data i nput waveforms........................................................................................ 43 14.1.2. data inpu t format.............................................................................................................. .. 44 14.1.3. 3-wire timing diagr am......................................................................................................... 4 6 14.1.4. output timing diagra m........................................................................................................ 46 15. pin assignment (i c face view).................................................................................................. ................. 47 15.1. pad locat ion ................................................................................................................... ............... 48 16. bump mask in formation .......................................................................................................... .................... 58 17. color filter arrangement ....................................................................................................... ...................... 59 18. revision hi story ............................................................................................................... ........................... 60 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 3 of 60 1. introduction ili6480b is one-chip solution for a-tft lcd panel. the panel application is focused on the resolution of 480rgbx272. the source driver, gate driver, built-in pow er generator and timing controller are integrated in the ili6480b. the serial communication interface is also implemented for the register setting. this chip can operates in a wide range of supply voltage. by applying ?dual gate driver? panel architecture, the number of source output is reduced to 720 channels and the number of gate output is increased to 544 channel s. for the concern of lowe r power dissipation, line inversion driving technique was adopted. with dithering technique applied, source output support 8-bit resolution and 256-gray scale with small output deviation are designed to support higher color resolution. 2. features ? generate 720x544 tft control signals with timing controller ? panel resolution(hxv): 480[rgb]x272 ? 8-bit resolution 256 gray scale with dithering(7bits dac + 1 bit frc) ? display control and function select by 3-wire serial communication control. ? build-in dc/dc charge pump, regulator and vcom with programmable adjustment ? source output deviation: 20mv ? line inversion or half-line inversion selectable ? right/left shift, up and down scan function selectable ? build-in pwm circuit for led backlight ? power for digital circuit(vdd): 2.7v~ 3.6v ? power for analog circuit(pvdd): 2.7v ~ 3.6v ? power for interface (vddio): 1.8v ~ 3.6v http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 4 of 60 3. block diagram http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 5 of 60 4. application block ili6480 dum g2 g4 g6 g540 g542 g544 com2_r com2_r com2_r com2_r com2_r s1 s2 s3 s358 s359 s360 dcmp dcmp dcmp dcmp dcmp dcmp dcmp dcmp s361 s362 s363 s718 s719 s720 com1_r com1_r com1_r com1_r com1_r g543 g541 g539 g5 g3 g1 dum dum shielding10 vgl c4m c4p vgh c3m c3p shielding9 vint2 c2m c2p pvdd c1cm c1cp c1bm c1bp c1am c1ap com2_l pgnd vint1 c5p c5m vint3 shielding8 agnd avdd shielding7 db7 db6 db5 db4 db3 db2 db1 db0 dg7 dg6 dg5 dg4 dg3 dg2 dg1 dg0 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 shielding6 cpsel pinctl shlr updn hvdsl grb stb scl/ cabc_mode1 sda/ cabc_mode0 csb/reserved psel den dclk hsd vsd vdd vddio vcc gnd drv shielding5 fb shielding4 dum vcom vcoml vcomh shielding3 com1_l shielding2 vpp otp tcsw1 tcsw0 tb1 tb0 (pwm_out) clkpol hsdpol vsdpol dithb fpol shdb ext_pwr lhl tb3 tb2 tm3 tm2 rbswp dswp tp10 tp9 tp8 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 shielding1 dum (1) (1) (3) (2) (2) (3) (2) (2) (1) (3) (2) (2) (8) (3) (3) (3) (3) (3) (3) (2) (8) (6) (3) (3) (4) (1) (6) (6) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (3) (3) (3) (3) (2) (1) (1) (1) (3) (6) (3) (3) (1) (2) (1) (3) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) display area (top view) 1440 x 272 g2 g4 g6 g540 g542 g544 s1 s2 s3 s718 s719 s720 720ch g1 g3 g5 g539 g541 g543 272ch 272ch gnd dr[7:0] dg[7:0] db[7:0] dclk vsd hsd den csb scl sda stb vdd gnd agnd pvdd pgnd schottky diode turn on voltage<0.3v 2.2uf/16v 2.2uf/25v 2.2uf/16v 1uf/16v 4.7uf/6v 2.2uf/6v 4.7uf/10v 2.2uf/6v 2.2uf/6v 4.7uf/10v 2.2uf/6v 2.2uf/6v optional: rc delay for reset vddio vddio vdd pvdd 1uf/16v 1uf/16v 2.2uf/6v 2.2uf/6v 4.7uf/10v 4.7uf/10v 4.7uf/10v http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 6 of 60 5. charge pump circuit block charge pump 1 c1ap c1am c1bp c1bm c1cm c1cp pvdd vint1 (<=6.5v) regulator avdd (5.6v) charge pump 2 vint2 c2m c2p charge pump 3 vgh (16 ~ 19v) c3m c3p charge pump 4 vgl (-4 ~ -7v) c4m c4p vcom adjust circuit pol control signal vcom vcomh vcoml regulator vcc (1.8v) vdd charge pump 5 vint3 (-2.7 ~ -3.6v ) c5m c5p http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 7 of 60 6. pin descriptions pin name i/o descriptions hsd i (vddio) horizontal sync input. negative polarity. *remark: internal pulled weak high vsd i (vddio) vertical sync input. negative polarity. *remark: internal pulled weak high dclk i (vddio) clock signal. latching data at the rising edge den i (vddio) data input enable. active high to enable the data input bus under ?de mode?. *remark: internal pulled weak low psel i (vddio) parallel 24-bit and serial 8-bit data input selection. psel=?h?, parallel 24-bit rgb input th rough dr[7:0], dg[7:0], db[7:0], psel=?l?, serial 8-bit dat a input through dr[7:0] *remark: internal pulled weak high dr[7:0] i (vddio) when psel=?h?, these will be treated as parallel 8-bit digital red data input. when psel=?l?, these will be treated as serial 8-bit data input. *remark: internal pulled weak low dg[7:0] i (vddio) 8-bit digital green data input, only va lid when psel=?h? (parallel mode). *remark: internal pulled weak low db[7:0] i (vddio) 8-bit digital blue data input, only valid when psel=?h? (parallel mode). *remark: internal pulled weak low csb i (vddio) multi function control pin. when tb1=?l?, this pin act as 3-wire ?csb? pin when tb1=?h?, reserved. * remark: internal pulled weak high sda i/o (vddio) multi function control pin. when tb1=?l?, this pin act as 3-wire ?sda? pin. when tb1=?h?, this pin act as cabc mode select pin lsb (cabcm[0]) * remark: internal pulled weak low scl i (vddio) multi function control pin. when tb1=?l?, this pin act as 3-wire ?scl? pin. when tb1=?h?, this pin act as cabc mode select pin msb (cabcm[1]) cabcm[1:0] = 00b, off (default) cabcm[1:0] = 01b, user interface image cabcm[1:0] = 10b, still picture cabcm[1:0] = 11b, moving image *remark: internal pulled weak low stb i (vddio) standby setting for testing, it should be c onnected to vddio in normal operation mode. if connected to gnd, the ic is in standby mode. *remark: internal pulled weak high grb i (vddio) global reset pin, it should be connect ed to vddio in normal operating mode. if connected to gnd, the timing cont roller is in reset state, suggest to be connected with a rc reset circuit for stability. *remark: internal pulled weak high hvdsl i (vddio) hv mode or de mode control signal. hvdsl=?h?: set under hv mode, vsd and hsd signal have to provide by system. hvdsl=?l?: set under de mode, de signal have to provide by system. *remark: internal pulled weak low updn i (vddio) gate driver up/down scan control of gate driver. updn=?h?, shift from up to down, first line=l1->l2-> ? ->l543->l544=last line updn=?l?, shift from down to up, first line=l544->l543-> ? ->l2->l1=last line *remark: internal pulled weak high shlr i (vddio) right/left sequence control of source driver. shlr=?h?, shift right: first data=s1->s2->s3 ? ->s720=last data shlr=?l?, shift left: last data=s1<-s2<-s3 ? <-s720=first data *remark: internal pulled weak high http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 8 of 60 pin name i/o descriptions tb0 (pwm_out) o (vddio) pwm output control signal for cabc function tb1 i (vddio) cabc/3-wire selection pin tb1=?h?, select cabc hardware control function. tb1=?l?, select 3-wire spi interface function. *remark: internal pulled weak low pinctl i (vddio) enable pin control function pinctl=?h?, enable pin control function pinctl=?l?, disable pin control function *remark: internal pulled weak low note: the 3-wire related control register will be disabled under pinctl=?h? cpsel i (vddio) charge pump structure select pin. cpsel=?h?, c1cp/m is connected to capacitor.. cpsel=?l?, c1cp/m is floating *remark: internal pulled weak low ext_pwr i (vddio) external power control pin. ext_pwr=?h?: vint1 could be input externally. ext_pwr=?l?: vint1 is generated by charge pump circuit. *remark: internal pulled weak low vsdpol i (vddio) vsd polarity control pin. vsdpol=?h?: vsd positive polarity. vsdpol=?l?: vsd negative polarity. *remark: internal pulled weak low hsdpol i (vddio) hsd polarity control pin. vsdpol=?h?: hsd positive polarity. vsdpol=?l?: hsd negative polarity. *remark: internal pulled weak low clkpol i (vddio) dclk polarity control pin. clkpol=?h?: data sampling at dclk falling edge. clkpol=?l?: data sampling at dclk rising edge. *remark: internal pulled weak low fpol i (vddio) vcom polarity inverse control pin. when fpol=?h?, vcom inverse polarity. when fpol=?l?, vcom normal polarity. *remark: internal pulled weak low dithb i (vddio) dithering control pin. dithb=?h?, dithering off, (7-bit s resolution, truncation last 1-bits of the input data) dithb=?l?, dithering on, (pseudo 8-bits resolution). *remark: internal pulled weak low shdb i (vddio) shut down for back light power converter. stdb=?h?, the back light power converter is controlled by stb?s power on/off sequence stdb=?l?, the back light power converter is off. *remark: internal pulled weak low lhl i (vddio) line/half-line inversion control pin. lhl=?h?, half line inversion. (default) lhl=?l?, line inversion. *remark: internal pulled weak high fb i main boost regulator feedback input. co nnect feedback resistive divider to gnd. fb threshold is 0.6v nominal. drv o power transistor gate signal for the boost converter. vdd p power supply for digital circuits gnd p ground for digital circuits. pvdd p power supply for analog circuits. pgnd p ground pin for power circuits. agnd p ground pin for analog circuits. vddio p power supply for logic i/o. vpp_otp p customer otp power input pin. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 9 of 60 pin name i/o descriptions vcc c capacitor connect pin for internal regulator. avdd c power setting capacitor connect pin. vint1 c power setting capacitor connect pin. vint2 c power setting capacitor connect pin. vint3 c power setting capacitor connect pin. vgh c power setting capacitor connect pin. vgl c power setting capacitor connect pin. c1ap/m c1bp/m c1cp/m c2p/m c3p/m c4p/m c5p/m c capacitor connect pin for internal charge pump. refer to the section of ?power circuit? for the application. vcom o panel common plate output. vcomh c power supply for panel common plate high level output. vcoml c power supply for panel common plate low level output. s720 ~ 1 o source driver output signals. g544 ~ 1 gate driver output signals. dcmp o test pin. please let this pin open. align_r align_l m for assembly alignment. com1_l com1_r s the internal link together between input side and output side. com2_l com2_r s the internal link together between input side and output side. dswp i data sequence control pin. when dswp=?h?, swap data sequence. when dswp =?l?, normal data sequence. *remark: internal pulled weak low rbswp i r/b swap control pin. when rbswp =?h?, r ? b, b ? r when rbswp =?l?, normal data. *remark: internal pulled weak low tp[10:0] t test pins for internal testing only. *remark: not connected. tcsw0 i (vddio) enable pin control funciotn. tcsw0=0 : vcom frequency is fixed. tcsw0=1 : split the vcom frequency. *remark : internal pulled weak high tcsw1 i (vddio) test pins for internal testing only. *remark : internal pulled weak high tb2 t gate scan select function. tb2=?h?, bow scan method.. tb2=?l?, z inversion z scan method. (default) *remark: internal pulled weak low tb3 t test pins for internal testing only. leave this pin to be open. *remark : not connection. tm2 t test pins for internal testing only. leave this pin to be open. *remark : not connection. tm3 t test pins for internal testing only. leave this pin to be open. *remark : not connection. shielding s this pin is internal floating. *remark: not connected. dum d dummy pads. leave this pin to be open. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 10 of 60 note: i: input, o: output, p: power, d: dummy, s: shorted line, m: mark, pi: power input, po: power output, t: testing i/ o: input / output. ps: power setting, c: capacitor pin. pass line description: pass line no. pad name 1 com1_l com1_r 2 com2_l com2_r http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 11 of 60 7. 3-wire serial interface ili6480b uses the 3-wire serial interface to set all t he function and register parameter. the 3-wire serial interface is bi-directional a nd controlled by the r/w bit. in the read mode, 3-wire serial interface will return the read data during ?data phase?. the returned data should be latched at the rising edge of scl by external controller. data in the ?hi-z phase ? will be ignored. during read operation, external controller should float sda pin under the ?hi-z phase? and ?data phase?. each read/write operation should be exactly 16 bit to pr event from incorrect setting of the internal register; any write operation with more or less than 16 bit data dur ing a csb low period will be ignored by 3-wire serial interface. csb sda scl d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 address[5:0] w/r hi-z data[7:0] delay next transfer bit description d[15:10] register address [5:0]. d9 w/r control bit. ?0? for write; ?1? for read d8 hi-z bit during read mode. any data within this bits will be ignored during write mode d[7:0] data for the w/r operatio n to the address indicated by addr ess phase note: setting of all the registers will take effect at t he coming falling edge of vsd signal except resetb and stbyb bit. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 12 of 60 8. register list address r/w parameter data n0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w hsdpol vsdpol clkpol fpol nfsel frad1 frad0 dithb r0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 r/w cabc_ mode1 cabc_ mode0 x lhl stb grb shrl updn r1 0 0 0 0 0 1 0 x 0 0 x 1 1 1 1 1 r/w x vfbsel drv_freq pwm_duty[2:0] shdb r2 0 0 0 0 1 0 0 x x 0 1 0 0 1 1 0 r/w led_on_cycle[3:0] led_on_ratio[3:0] r3 0 0 0 0 1 1 0 x 0 1 1 1 1 1 1 1 r/w ddl[7:0] r4 0 0 0 1 0 0 0 x 0 0 1 0 1 0 0 0 r/w x x x hdl[4:0] r5 0 0 0 1 0 1 0 x x x x 0 1 0 0 0 r/w vcomh_otp vcomh [6] vcomh [5] vcomh [4] vcomh [3] vcomh [2] vcomh [1] vcomh [0] r6 0 0 0 1 1 0 0 x 0 1 0 0 1 1 0 1 r/w vcoml_otp vcoml [6] vcoml [5] vcoml [4] vcoml [3] vcoml [2] vcoml [1] vcoml [0] r7 0 0 0 1 1 1 0 x 0 0 1 0 1 0 0 0 r/w bri[7:0] r8 0 0 1 0 0 0 0 x 0 1 0 0 0 0 0 0 r/w con_b[7:0] r9 0 0 1 0 0 1 0 x 0 1 0 0 0 0 0 0 r/w x sub_bri_r[6:0] r10 0 0 1 0 1 0 0 x x 1 0 0 0 0 0 0 r/w x sub_con_r[6:0] r11 0 0 1 0 1 1 0 x x 1 0 0 0 0 0 0 r/w x sub_bri_b[6:0] r12 0 0 1 1 0 0 0 x x 1 0 0 0 0 0 0 r/w x sub_con_b[6:0] r13 0 0 1 1 0 1 0 x x 1 0 0 0 0 0 0 r/w x x v2gam[3:0] gamen x r14 0 0 1 1 1 0 0 x x x 1 0 0 0 1 x r/w v4gam[3:0] v3gam[3:0] r15 0 0 1 1 1 1 0 x 1 0 0 0 1 0 0 0 r/w v6gam[3:0] v5gam[3:0] r16 0 1 0 0 0 0 0 x 1 0 0 0 1 0 0 0 r/w v8gam[3:0] v7gam[3:0] r17 0 1 0 0 0 1 0 x 1 0 0 0 1 0 0 0 r/w x x x x v9gam[3:0] r18 0 1 0 0 1 0 0 x x x x x 1 0 0 0 r/w x x x x vgl_sel[1:0] vgh_sel[1:0] r19 0 1 0 0 1 1 0 x x x x x 1 1 1 0 r/w trmen[7:0] r20 0 1 0 1 0 0 0 x 0 0 0 0 0 0 0 0 r/w v13gam[3:0] v12gam[3:0] r21 0 1 0 1 0 1 0 x 1 0 0 0 1 0 0 0 r/w v15gam[3:0] v14gam[3:0] r22 0 1 0 1 1 0 0 x 1 0 0 0 1 0 0 0 r/w v17gam[3:0] v16gam[3:0] r23 0 1 0 1 1 1 0 x 1 0 0 0 1 0 0 0 r/w v19gam[3:0] v18gam[3:0] r24 0 1 1 0 0 0 0 x 1 0 0 0 1 0 0 0 r/w dbv[7:0] r30 0 1 1 1 1 0 1 x 1 1 1 1 1 1 1 1 w x x bctl x dd bl x x r32 1 0 0 0 0 0 1 x x x 1 x 1 1 x x r x x bctl x dd bl x x r33 1 0 0 0 0 1 1 x x x 1 x 1 1 x x http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 13 of 60 w x x x x x x x x r34 1 0 0 0 1 0 1 x x x x x x x x x r x x x x x x x x r35 1 0 0 0 1 1 1 x x x x x x x x x w cmb[7:0] r36 1 0 0 1 0 0 1 x 0 0 0 0 0 0 0 0 r cmb[7:0] r37 1 0 0 1 0 1 1 x 0 0 0 0 0 0 0 0 w pwm_div[7:0] r38 1 0 0 1 1 0 1 x 0 0 0 0 1 1 1 1 w thres_mov[3:0] thres_still[3:0] r39 1 0 0 1 1 1 1 x 1 1 0 0 1 1 0 0 w x x x x thres_ui[3:0] r40 1 0 1 0 0 0 1 x x x x x 1 1 0 0 w min-dth_mov[3:0] min-dth_still[3:0] r41 1 0 1 0 0 1 1 x 0 1 1 0 1 0 0 1 w x x x x min-dth_ui[3:0] r42 1 0 1 0 1 0 1 x x x x x 0 1 0 0 w dim_opt2[3:0] x dim_opt1[2:0] r43 1 0 1 0 1 1 1 x 0 1 1 1 x 1 0 0 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 14 of 60 register r0 bit d7 d6 d5 d4 d3 d2 d1 d0 name hsdpol vsdpol clkpol fpol nfsel frad1 frad0 dithb default 0 0 0 0 0 0 0 0 dithb : dithering control bit. dithb=?1?, dithering function is disabled, (7-bits re solution, truncation last 1- bits of the input data) dithb=?0?, dithering function is enabled, (pseudo 8-bits resolution). (default) frad[1:0] : odd / even frame advance control. frad shoul d be correctly configured if the hbp of even-frame and odd-frame of incoming data are diffe rent. there are three examples for frad setting reference. example 1: if hbp in odd-frame is 21 and hbp in ev en-frame is 21, then frad should be set to 0 and hdl should be set to 21. example 2: if hbp in odd-frame is 21 and hbp in even-frame is 22 (odd frame advance), then frad should be set to 1 and hdl should be set to 21. example 3: if hbp in odd-frame is 21 and hbp in ev en-frame is 20 (even frame advance), then frad should be set to 2 and hdl should be set to 20. frad1 frad0 descriptions notes 0 0 default odd/even frame tstv are the same 0 1 odd frame advance even frame tstv = hdl setting +1 1 0 even frame advance odd frame tstv = hdl setting +1 1 1 reserved reserved nfsel : narrow display mode selection bit. nfsel=?1?: narrow display format is enabled. nfsel=?0?: normal display is selected. (default) fpol : vcom polarity inverse control bit. fpol=?1?, vcom inverse polarity. fpol=?0?, vcom normal polarity. (default) clkpol : dclk polarity control bit. clkpol=?1?: data is latched at dclk falling edge. clkpol=?0?: data is latched at dclk rising edge. (default) http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 15 of 60 vsdpol : vsd polarity control bit. vsdpol=?1?: vsd positive polarity. vsdpol=?0?: vsd negative polarity. (default) hsdpol : hsd polarity control bit. vsdpol=?1?: hsd positive polarity. vsdpol=?0?: hsd negative polarity. (default) register r1 bit d7 d6 d5 d4 d3 d2 d1 d0 name cabc_mode[1] cabc_mod e[0] x lhl stb grb shrl updn default 0 0 1 1 1 1 1 updn : gate driver up/down scan direction control updn=?1?, gate signal shift from up to down, l1 (1 st line) ? l2 ? ? ? l543 ? l544 (last line) (default) updn=?0?, gate signal shift from down to up, l544 (1 st line) ? l543 ? ? ? l2 ? l1 (last line) shrl : right/left sequence control of source driver. shlr=?1?, shift right: first data=s1 ? s2 ? s3 ? ? s720=last data (default) shlr=?0?, shift le ft: last data=s1, ? s2 ? s3 ? ? s720=first data grb : global reset bit. grb=?1?, normal operation. (default) grb=?0?, the controller is in reset state. stb : standby mode selection bit. stb=?1?, normal operation. (default) stb=?0?, standby mode. lhl : line/half-line inversion selection bit. lhl=?1?, half line inversion. (default) lhl=?0?, line inversion. cabc_mode1/0: cabc operation mode selection cabc_mode[1:0] description 0 cabc off 1 user interface image 2 still picture 3 moving image http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 16 of 60 register r2 bit d7 d6 d5 d4 d3 d2 d1 d0 name x vfbsel[1:0] drv_freq pwm_duty[2:0] shdb default x 0 1 0 0 1 1 0 stdb : shut down the back light power converter. stdb=?1?, the back light power converter is controlled by stb?s power on/off sequence stdb=?0?, the back light power converter is off. (default) pwm_duty[2:0] : pwm duty cycle selection for back light power converts pwm_duty[2:0] pwm duty cycle 000 50% 001 60% 010 65% 011 70% 100 75% 101 80% 110 85% 111 90% drv_freq : drv signal frequency setting drv_freq=?1?, drv frequency is dclk/64. drv_freq=?0?, drv frequency is dclk/32. (default) vfbsel[1:0] : fb voltage adjustable for dc-dc feedback threshold vfbsel[1:0] feedback threshold voltage unit 00 0.75 01 0.60 (default) 10 0.45 11 0.30 volt http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 17 of 60 register r3 bit d7 d6 d5 d4 d3 d2 d1 d0 name led_on_cycle[3:0 ] led_on_ratio[3:0] default 0 1 1 1 1 1 1 1 led_on_ratio[3:0] : set the active ratio of enable signal, and we can use it to adjust brightness of the leds. led_on_ratio[3:0] value led_on_ratio[3:0] value 4?b0000 1/16 4?b1000 9/16 4?b0001 2/16 4?b1001 10/16 4?b0010 3/16 4?b1010 11/16 4?b0011 4/16 4?b1011 12/16 4?b0100 5/16 4?b1100 13/16 4?b0101 6/16 4?b1101 14/16 4?b0110 7/16 4?b1110 15/16 4?b0111 8/16 4?b1111 (default) 16/16 led_on_cycle[3:0] : set the active ratio of enable signal, and we can use it to adjust brightness of the leds. led_on_cycle[3:0] value led_on_cycle[3:0] value 4?b0000 1 4?b1000 9 4?b0001 2 4?b1001 10 4?b0010 3 4?b1010 11 4?b0011 4 4?b1011 12 4?b0100 5 4?b1100 13 4?b0101 6 4?b1101 14 4?b0110 7 4?b1110 15 4?b0111(default) 8 4?b1111 16 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 18 of 60 register r4 bit d7 d6 d5 d4 d3 d2 d1 d0 name ddl[7:0] default 0 0 1 0 1 0 0 0 ddl[7:0] : select the hsd signal to 1?st input data delay timing. ddl[7:0] ddl function unit 8?h00 setting prohibited 8?h01 setting prohibited ? ? 8?h24 setting prohibited 8?h25 37 8?h26 38 ? ? 8?h28 40(default setting for parallel mode) 8?h29 41 ? ? 8?h78 120(default setting for serial mode) 8?h79 121 ? ? 8?hff 255 dclk register r5 bit d7 d6 d5 d4 d3 d2 d1 d0 name x x x hdl[4:0] default x x x 0 1 0 0 0 hdl[4:0] : select the gate start pulse output delay timing. hdl[4:0] hdl function unit 5?h00 setting prohibited ? ? 5?h05 5 ? ? 5?h08 8 (default) ? ? 5?h1f 31 hsd register r6 bit d7 d6 d5 d4 d3 d2 d1 d0 name vcomh_otp vcomh[6] vcomh[5] vcomh[4] vc omh[3] vcomh[2] vcomh[1] vcomh[0] default 0 1 0 0 1 1 0 1 vcomh[6:0]: set the vcomh voltage (20mv/lsb). vcomh[6:0] vcomh voltage unit 7?b00h 2.46 7?b01h 2.48 ? ? 7?b1bh 3 7?b1ch 3.02 ? ? 7?b4dh 4 (default) 7?b4eh 4.02 ? ? 7?b7fh 5 volt http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 19 of 60 vcomh_otp: vcomh_otp =?1?, vcomh is switched to the 3-wire register memory when the user wants to adjust the vcomh level. vcomh_otp =?0?, vcomh is read from otp memory. (default) register r7 bit d7 d6 d5 d4 d3 d2 d1 d0 name vcoml_otp vcoml[6] vcoml[5] vcom l[4] vcoml[3] vcoml[2] vcoml[1] vcoml[0] default 0 0 1 0 1 0 0 0 vcoml[6:0]: set the vcoml voltage (20mv/lsb). vcoml[6:0] vcoml voltage unit 7?b00h -0.46 7?b01h -0.48 ? ? 7?b27h -1.24 7?b28h -1.26(default) ? ? 7?b4dh -2 7?b4eh -2.02 ? ? 7?b7fh -3 volt vcoml_otp: vcoml_otp =?1?, vcoml is switched to the 3-wire register memory when the user wants to adjust the vcomh level. vcoml_otp =?0?, vcoml is read from otp memory. (default) register r8 bit d7 d6 d5 d4 d3 d2 d1 d0 name bri[7:0] default 0 1 0 0 0 0 0 0 bri[7:0] : brightness level setting, the gain changes 1 step/bit bri[7:0] brightness offset 8?h00 dark (-64) 8?h01 -63 ? ? 8?h40 center (0, default) ? ? 8?hff bright (+191) http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 20 of 60 register r9 bit d7 d6 d5 d4 d3 d2 d1 d0 name con[7:0] default 0 1 0 0 0 0 0 0 con[7:0] : contrast level setting, the gain changes (1/64)/bit con[7:0] contrast gain 8?h00 0 8?h01 1/64 ? ? 8?h40 1 (default) ? ? 8?hff 3.984 register r10 bit d7 d6 d5 d4 d3 d2 d1 d0 name x sub_bri_r[6:0] default x 1 0 0 0 0 0 0 sub_bri_r[6:0] : red sub-pixel brightness level setting, setting accuracy: 1 step/bit sub_bri_r[6:0] red brightness offset 7?h00 dark (-64) 7?h01 -63 ? ? 7?h40 center (0) (default) ? ? 7?h7f bright (+63) register r11 bit d7 d6 d5 d4 d3 d2 d1 d0 name x sub_con_r[6:0] default x 1 0 0 0 0 0 0 sub_con_r[6:0] : red sub-pixel contrast level setting, the gain changes (1/256)/bit sub_con_r[6:0] red contrast gain 7?h00 0.75 7?h01 0.75+ 1/256 ? ? 7?h40 1 (default) ? ? 7?h7f 1.246 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 21 of 60 register r12 bit d7 d6 d5 d4 d3 d2 d1 d0 name x sub_bri_b[6:0] default x 1 0 0 0 0 0 0 sub_ bri _b[6:0] : blue sub-pixel contrast level setting, the gain changes (1/256)/bit sub_bri_b[6:0] blue brightness offset 7?h00 dark (-64) 7?h01 -63 ? ? 7?h40 center (0) (default) ? ? 7?h7f bright (+63) register r13 bit d7 d6 d5 d4 d3 d2 d1 d0 name x sub_con_b[6:0] default x 1 0 0 0 0 0 0 sub_con_b[6:0] : blue sub-pixel contrast level setting, the gain changes (1/256)/bit sub_con_b[6:0] blue contrast gain 7?h00 0.75 7?h01 0.75+ 1/256 ? ? 7?h40 1 (default) ? ? 7?h7f 1.246 register r14 bit d7 d6 d5 d4 d3 d2 d1 d0 name x x v2gam[3:0] gamen x default x x 1 0 0 0 1 - gamma adjustment enable control bit.(adjustable voltage for v2-v9 and v12-v19) gamen =?1?, gamma correction enabled gamen =?0?, gamma correction disabled. v2gam[3:0] : v2 gamma voltage level setting. adjust level = 20mv / step register r15 bit d7 d6 d5 d4 d3 d2 d1 d0 name v4gam[3:0] v3gam[3:0] default 1 0 0 0 1 0 0 0 v3gam[3:0] : v3 gamma voltage level setting. adjust level = 20mv / step v4gam[3:0] : v4 gamma voltage level setting. adjust level = 20mv / step register r16 bit d7 d6 d5 d4 d3 d2 d1 d0 name v6gam[3:0] v5gam[3:0] default 1 0 0 0 1 0 0 0 v5gam[3:0] : v5 gamma voltage level setting. adjust level = 20mv / step v6gam[3:0] : v6 gamma voltage level setting. adjust level = 20mv / step http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 22 of 60 register r17 bit d7 d6 d5 d4 d3 d2 d1 d0 name v8gam[3:0] v7gam[3:0] default 1 0 0 0 1 0 0 0 v7gam[3:0] : v7 gamma voltage level setting. adjust level = 20mv / step v8gam[3:0] : v8 gamma voltage level setting. adjust level = 20mv / step register r18 bit d7 d6 d5 d4 d3 d2 d1 d0 name x x x x v9gam[3:0] default x x x x 1 0 0 0 v9gam[3:0] : v9 gamma voltage level setting. adjust level = 20mv / step vxgam[3:0] gamma voltage unit note 4?h0 +160 4?h8 vxgam[3:0] (default) 4?hf -140 mv refer to the gamma table for the default voltage level of v2~ v9 register r19 bit d7 d6 d5 d4 d3 d2 d1 d0 name x x x x vgl_sel[1:0] vgh_sel[1:0] default x x x x 1 1 1 0 vgh_sel[1:0] : vgh output voltage selection vgh_sel[1:0] vgh voltage unit 2?b00 16 2?b01 17 2?b10 18(default) 2?b11 19 volt vgl_sel[1:0] : vgl output voltage selection vgl_sel[1:0] vgl voltage unit 2?b00 -4 2?b01 -5 2?b10 -6 2?b11 -7 (default) volt register r20 bit d7 d6 d5 d4 d3 d2 d1 d0 name trmen[7:0] default 0 0 0 0 0 0 0 0 trmen[7:0] : vcomh and vcoml trim function control register. write the following command sequentially to enable the vdv[4:0] and vmc[4:0] trim function. adjust vcomh level: set trmen[7:0]=00h and write proper vcomh[6: 0] value by the 3-wire spi interface. programming the vcomh[6:0] value into otp memory: set trmen[7:0] as following sequence a0h->5fh->eeh->00h vcomh_otp will be clear to 0b after the progra mming procedure. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 23 of 60 note: 1. the trim block can be written for only 2 times. trim command exceed the limit may cause the vcomh/vcoml output unknown value. 2. vcomh_otp or vcoml_otp will be clear to 0b after the programming procedure. procedure 1 set vpp_otp=6.0v procedure 2 set vcomh_otp=1 procedure 3 set vcomh[6:0] procedure 4 set trmen[7:0] as following sequence a0h -> 5fh -> eeh -> 00h to write the vcomh[6:0] value into otp memory procedure 5 wait 20ms to comple te otp programming and restart ili6480 vcomh otp program start procedure 1 set vpp_otp=6.0v procedure 2 set vcoml_otp=1 procedure 3 set vcoml[6:0] procedure 4 set trmen[7:0] as following sequence a0h -> 5fh -> eeh -> 00h to write the vcoml[6:0] value into otp memory procedure 5 wait 20ms to comple te otp programming and restart ili6480 vcoml otp program start http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 24 of 60 register r21 bit d7 d6 d5 d4 d3 d2 d1 d0 name v13gam[3:0] v12gam[3:0] default 1 0 0 0 1 0 0 0 v12gam[3:0] : v12 gamma voltage level setting. adjust level = 20mv / step v13gam[3:0] : v13 gamma voltage level setting. adjust level = 20mv / step register r22 bit d7 d6 d5 d4 d3 d2 d1 d0 name v15gam[3:0] v14gam[3:0] default 1 0 0 0 1 0 0 0 v14gam[3:0] : v14 gamma voltage level setting. adjust level = 20mv / step v15gam[3:0] : v15 gamma voltage level setting. adjust level = 20mv / step register r23 bit d7 d6 d5 d4 d3 d2 d1 d0 name v17gam[3:0] v16gam[3:0] default 1 0 0 0 1 0 0 0 v16gam[3:0] : v16 gamma voltage level setting. adjust level = 20mv / step v17gam[3:0] : v17 gamma voltage level setting. adjust level = 20mv / step register r24 bit d7 d6 d5 d4 d3 d2 d1 d0 name v19gam[3:0] v18gam[3:0] default 1 0 0 0 1 0 0 0 v18gam[3:0] : v18 gamma voltage level setting. adjust level = 20mv / step v19gam[3:0] : v19 gamma voltage level setting. adjust level = 20mv / step http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 25 of 60 register r30 (read/write display brightness value) bit d7 d6 d5 d4 d3 d2 d1 d0 name dbv[7:0] default 1 1 1 1 1 1 1 1 dbv[7:0] : this command is used to adjust the brightness va lue of the display.pwm_out signal?s pulse duty is selected from 256 values between 8'hff and 8'h00 to adjust the led brightness.. when this register is read back, the led brightness data for pwm_out signal is read by baseband and basenabd can adjust the backlight brightness based the read back dbv value. register r32 (write ctrl display) bit d7 d6 d5 d4 d3 d2 d1 d0 name x x bctl x dd bl x x default x x 1 x 1 1 x x x: don?t care bctrl : brightness control block on/off. bctrl description 0 brightness control block off (dbv[7:0]=00h) 1 brightness control block on (dbv[7:0] is active) dd : display dimming control. this function is only fo r manual brightness setting. when the cabc is enabled, the dimming function is controlled by cabc block automatically. dd description 0 display dimming off (changes immediately) 1 display dimming on (changes gradually base on the r43h register setting) bl : backlight control (pwm_out signal) on/off bl description 0 backlight control off 1 backlight control on when bl bit change from ?on? to ?off?, backlight is turned off without gradual dimming, even if dimming-on (dd=1) are selected. register r33 (read ctrl display) bit d7 d6 d5 d4 d3 d2 d1 d0 name x x bctl x dd bl x x default x x 1 x 1 1 x x x: don?t care this command is used to read the ctrl register. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 26 of 60 register r36 (write cabc minimum brightness) bit d7 d6 d5 d4 d3 d2 d1 d0 name cmb[7:0] default 0 0 0 0 0 0 0 0 this command is used to set the minimum bright ness value of the display for cabc function. cmb[7:0] : this register is used to limit the brightness reduction. when cabc function is enabled, the display brightness can?t be reduced to exceed the cabc minimum brightness setting. when the cabc function is disabled (r34h=00h), cabc minimum brightness setting is ignored and user can set the dbv[7:0] smaller than cmb[7:0] value. register r37 (read cabc minimum brightness) bit d7 d6 d5 d4 d3 d2 d1 d0 name cmb[7:0] default 0 0 0 0 0 0 0 0 this command is used to read the minimum brightness value of the display for cabc function. register r38 (cabc control 1) bit d7 d6 d5 d4 d3 d2 d1 d0 name pwm_div[7:0] default 0 0 0 0 1 1 1 1 pwm_div[7:0] : pwm_out output frequency control. the pwm_ out frequency can be calculated by the following equation and the duty is based on the cabc result. f pwm_out = 255 ) 1 ] 0 : 7 [ _ ( 9 + div pwm mhz pwm_div[7:0] f pwm_out 8?0h 31.37 khz 8?1h 15.69 khz 8?2h 10.46khz 8?3h 7.843 khz ? ? 8?fh 2.026khz ? ? 8?fch 140hz 8?fdh 139hz 8?feh 138hz 8?ffh 137hz http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 27 of 60 pwm_out f pwm_out t on t off note : the output frequency tolerance of internal frequency divider in cabc is 10% register r39 (cabc control 2) bit d7 d6 d5 d4 d3 d2 d1 d0 name thres_mov[3:0] thres_still[3:0] default 1 1 0 0 1 1 0 0 thres_mov[3:0] : these bits are used to set the per centage of grayscale data accumulate histogram value in the moving picture mode. this ratio of maximum number of pixels that makes disp lay image white (=data ?255?) to the total of pixels by image processing. thres_mov[3:0] de scription thres_mo v[3:0] description 4?0h 99% 4?8h 84% 4?1h 98% 4?9h 82% 4?2h 96% 4?ah 80% 4?3h 94% 4?bh 78% 4?4h 92% 4?ch 76% 4?5h 90% 4?dh 74% 4?6h 88% 4?eh 72% 4?7h 86% 4?fh 70% thres_still[3:0] : these bits are used to set the per centage of grayscale data accumulate histogram value in the still picture mode. this ratio of maximum number of pixels that makes disp lay image white (=data ?255?) to the total of pixels by image processing. thres_still[3:0] description thres_still[3:0] description 4?0h 99% 4?8h 84% 4?1h 98% 4?9h 82% 4?2h 96% 4?ah 80% 4?3h 94% 4?bh 78% 4?4h 92% 4?ch 76% 4?5h 90% 4?dh 74% 4?6h 88% 4?eh 72% 4?7h 86% 4?fh 70% http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 28 of 60 register r40 (cabc control 3) bit d7 d6 d5 d4 d3 d2 d1 d0 name x x x x thres_ui[3:0] default x x x x 1 1 0 0 x: don?t care thres_ui[3:0] : these bits are used to set the pe rcentage of grayscale data accumulate histogram value in the user interface (ui) mode. this ratio of maximum number of pixels that makes disp lay image white (=data ?255?) to the total of pixels by image processing. thres_ui[3:0] description thres_ui[3:0] description 4?0h 99% 4?8h 84% 4?1h 98% 4?9h 82% 4?2h 96% 4?ah 80% 4?3h 94% 4?bh 78% 4?4h 92% 4?ch 76% 4?5h 90% 4?dh 74% 4?6h 88% 4?eh 72% 4?7h 86% 4?fh 70% 100% histogram thres_mov[3:0] thres_still[3:0] thres_ui[3:0] dth 255 gray scales http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 29 of 60 register r41 (cabc control 4) bit d7 d6 d5 d4 d3 d2 d1 d0 name min-dth_mov[3:0] min-dth_still[3:0] default 0 1 1 0 0 1 0 1 min-dth_mov[3:0] : this parameter is used set the minimum limitation of grayscale threshold value in moving image mode. this register setting will limit t he minimum dth value to prevent the display image from being too white and the display quality is not accpetable. min-dth_mov[3:0] description min-dth_mov[3:0] description 4?0h 224 4?8h 192 4?1h 220 4?9h 188 4?2h 216 4?ah 184 4?3h 212 4?bh 180 4?4h 208 4?ch 176 4?5h 204 4?dh 172 4?6h 200 4?eh 168 4?7h 196 4?fh 164 min-dth_still[30] : this parameter is used set the minimum limit ation of grayscale threshold value in still image mode. this register setting will limit the minimum dth value to prevent the display image from being too white and the display quality is not accpetable. min-dth_still[3:0] descriptio n min-dth_still[3:0] description 4?0h 224 4?8h 192 4?1h 220 4?9h 188 4?2h 216 4?ah 184 4?3h 212 4?bh 180 4?4h 208 4?ch 176 4?5h 204 4?dh 172 4?6h 200 4?eh 168 4?7h 196 4?fh 164 transmittance min-dth 255 gray scales http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 30 of 60 register r42 (cabc control 5) bit d7 d6 d5 d4 d3 d2 d1 d0 name x x x x min-dth_ui[3:0] default x x x x 0 1 0 0 x: don?t care dth_ui[3:0] : this parameter is used set the minimum limitation of grayscale threshold value in user icon (ui) image mode. this register setting will limit the minimu m dth value to prevent the display image from being too white and the display quality is not accpetable. min-dth_ui[3:0] description min-dth_ui[3:0] description 4?0h 252 4?8h 220 4?1h 248 4?9h 216 4?2h 244 4?ah 212 4?3h 240 4?bh 208 4?4h 236 4?ch 204 4?5h 232 4?dh 200 4?6h 228 4?eh 196 4?7h 224 4?fh 192 register r43 (cabc control 6) bit d7 d6 d5 d4 d3 d2 d1 d0 name dim_opt2[3:0] x dim_opt1[2:0] default 0 1 1 1 x 1 0 0 x: don?t care dim_opt1[2:0] : this parameter is used to set the transition time of brightness level to avoid the sharp brightness transition on vision. dim_opt1[2:0] description 3?0h 1 frame 3?1h 1 frame 3?2h 2 frames 3?3h 4 frames 3?4h 8 frames 3?5h 16 frames 3?6h 32 frames 3?7h 64 frames brightness time dim_opt1[3:0] dim_opt1[3:0] brightness =a brightness =b brightness =c transition time transition time http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 31 of 60 dim_opt2[3:0] : this parameter is used to set the threshold of brightness change. when the brightness transition difference is smaller than dim_opt2[2:0] , the brightness transition will be ignored. for example: if | brightness b ? brightness a| < di m_opt2[2:0], the brightness transi tion will be ignored and keep the brightness a. http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 32 of 60 9. power on/off sequence in order to power on /off ili6480b correctly, please follow the following recommended power on /off sequence. 9.1. power on sequence output = 0v normal output = 0v white normal t por 2 frame 2 frames 2 frame vdd vsd stb (serial command) avdd,vint1 vgl vgh vcom source output vled 1 frame 2 frame 1 frame vint3 vint2 1 frame http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 33 of 60 9.2. power off sequence vint1 output = 0v normal output = 0v white normal 1 frame vdd vsd stb (serial command) vgl vgh vcom source output vled 1 frame 1 frame avdd,vint3 vint2 1 frame 1 frame 1 frame 1 frame http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 34 of 60 9.3. charge-pump circuit connection ili6480 charge pump circuit cpsel = h c1ap c1am c1bp c1bm c1cp c1cm vint1 c2p c2m vint2 c3p c3m vgh c4p c4m vgl c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 ili6480 charge pump circuit cpsel = l c1ap c1am c1bp c1bm c1cp c1cm vint1 c2p c2m vint2 c3p c3m vgh c4p c4m vgl c1 c2 c4 c5 c6 c7 c8 c9 c10 c5p c5m c12 regulator avdd c13 vint3 c11 vcc c14 vcom adjust circuit vcomh c15 vcoml c16 c5p c5m c12 regulator avdd c13 vint3 c11 vcc c14 vcom adjust circuit vcomh c15 vcoml c16 component value voltage proof c1 2.2uf 6v c2 2.2uf 6v c3 2.2uf 6v c4 4.7uf 10v c5 1.0uf 16v c6 2.2uf 16v c7 1.0uf 16v c8 2.2uf 25v c9 1.0uf 16v c10 2.2uf 16v c11 4.7uf 10v c12 2.2uf 6v c13 4.7uf 10v c14 2.2uf 6v c15 4.7uf 10v c16 4.7uf 10v http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 35 of 60 10. input data and output voltage source driver data output seque nce can be control by ?shlr?. output s1 s2 s3 ? s718 s719 s720 shlr =?1? 1 st data ? last data shlr =?0? last data ? 1 st data gate driver scan output sequence can be control by ?updn?. output g1 g2 g3 ? g542 g543 g544 updn =?1? 1 st data ? last data updn =?0? last data ? 1 st data the figure below shows the relationship between the input data and the output voltage. refer to the following pages for the relative resistor values and voltage calculation method. 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 0 10203040506070 v o u t ( v ) positive gamma (vcom=low) 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 0 10203040506070 v o u t ( v ) negative gamma (vcom=high) http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 36 of 60 input data and output voltage reference table data vcom=h res. # gamma voltage formula data vcom=l res. # gamma voltage formula 0 0.185v --- v1 0 4.225v --- v20 1 0.265v 300 v1+((v2-v1)*(300/5640)) 1 4.151v 340 v20+((v19-v20)*(340/6430)) 2 0.331v 250 v1+((v2-v1)*(550/5640)) 2 4.086v 300 v20+((v19-v20)*(640/6430)) 3 0.477v 550 v1+((v2-v1)*(1100/5640)) 3 3.951v 620 v20+((v19-v20)*(1260/6430)) 4 0.609v 500 v1+((v2-v1)*(1600/5640)) 4 3.820v 600 v20+((v19-v20)*(1860/6430)) 5 0.742v 500 v1+((v2-v1)*(2100/5640)) 5 3.689v 600 v20+((v19-v20)*(2460/6430)) 6 0.861v 450 v1+((v2-v1)*(2550/5640)) 6 3.581v 500 v20+((v19-v20)*(2960/6430)) 7 0.967v 400 v1+((v2-v1)*(2950/5640)) 7 3.472v 500 v20+((v19-v20)*(3460/6430)) 8 1.065v 370 v1+((v2-v1)*(3320/5640)) 8 3.389v 380 v20+((v19-v20)*(3840/6430)) 9 1.153v 330 v1+((v2-v1)*(3650/5640)) 9 3.302v 400 v20+((v19-v20)*(4240/6430)) 10 1.237v 320 v1+((v2-v1)*(3970/5640)) 1 0 3.230v 330 v20+((v19-v20)*(4570/6430)) 11 1.306v 260 v1+((v2-v1)*(4230/5640)) 1 1 3.160v 320 v20+((v19-v20)*(4890/6430)) 12 1.373v 250 v1+((v2-v1)*(4480/5640)) 1 2 3.104v 260 v20+((v19-v20)*(5150/6430)) 13 1.439v 250 v1+((v2-v1)*(4730/5640)) 1 3 3.045v 270 v20+((v19-v20)*(5420/6430)) 14 1.492v 200 v1+((v2-v1)*(4930/5640)) 1 4 2.995v 230 v20+((v19-v20)*(5650/6430)) 15 1.547v 210 v1+((v2-v1)*(5140/5640)) 1 5 2.947v 220 v20+((v19-v20)*(5870/6430)) 16 1.593v 170 v1+((v2-v1)*(5310/5640)) 1 6 2.903v 200 v20+((v19-v20)*(6070/6430)) 17 1.638v 170 v1+((v2-v1)*(5480/5640)) 1 7 2.860v 200 v20+((v19-v20)*(6270/6430)) 18 1.680v 160 v2 18 2.825v 160 v19 19 1.725v 170 v2+((v3-v2)*(170/1980)) 19 2.786v 180 v19+((v18-v19)*(180/2130)) 20 1.762v 140 v2+((v3-v2)*(310/1980)) 20 2.751v 160 v19+((v18-v19)*(340/2130)) 21 1.799v 140 v2+((v3-v2)*(450/1980)) 21 2.718v 150 v19+((v18-v19)*(490/2130)) 22 1.834v 130 v2+((v3-v2)*(580/1980)) 22 2.687v 140 v19+((v18-v19)*(630/2130)) 23 1.868v 130 v2+((v3-v2)*(710/1980)) 23 2.657v 140 v19+((v18-v19)*(770/2130)) 24 1.900v 120 v2+((v3-v2)*(830/1980)) 24 2.629v 130 v19+((v18-v19)*(900/2130)) 25 1.932v 120 v2+((v3-v2)*(950/1980)) 25 2.600v 130 v19+((v18-v19)*(1030/2130)) 26 1.961v 110 v2+((v3-v2)*(1060/1980)) 2 6 2.574v 120 v19+((v18-v19)*(1150/2130)) 27 1.990v 110 v2+((v3-v2)*(1170/1980)) 2 7 2.548v 120 v19+((v18-v19)*(1270/2130)) 28 2.017v 100 v2+((v3-v2)*(1270/1980)) 2 8 2.524v 110 v19+((v18-v19)*(1380/2130)) 29 2.043v 100 v2+((v3-v2)*(1370/1980)) 2 9 2.500v 110 v19+((v18-v19)*(1490/2130)) 30 2.067v 90 v2+((v3-v2)*(1460/1980)) 3 0 2.478v 100 v19+((v18-v19)*(1590/2130)) 31 2.091v 90 v2+((v3-v2)*(1550/1980)) 3 1 2.456v 100 v19+((v18-v19)*(1690/2130)) 32 2.115v 90 v2+((v3-v2)*(1640/1980)) 3 2 2.436v 90 v19+((v18-v19)*(1780/2130)) 33 2.139v 90 v2+((v3-v2)*(1730/1980)) 3 3 2.417v 90 v19+((v18-v19)*(1870/2130)) 34 2.160v 80 v2+((v3-v2)*(1810/1980)) 3 4 2.397v 90 v19+((v18-v19)*(1960/2130)) 35 2.184v 90 v2+((v3-v2)*(1900/1980)) 3 5 2.377v 90 v19+((v18-v19)*(2050/2130)) 36 2.205v 80 v3 36 2.360v 80 v18 37 2.226v 80 v3+((v4-v3)*(80/1230)) 37 2.342v 80 v18+((v17-v18)*(80/1230)) 38 2.247v 80 v3+((v4-v3)*(160/1230)) 38 2.325v 80 v18+((v17-v18)*(160/1230)) 39 2.268vv 80 v3+((v4-v3)*(240/1230)) 39 2.307v 80 v18+((v17-v18)*(240/1230)) 40 2.287v 70 v3+((v4-v3)*(310/1230)) 40 2.290v 80 v18+((v17-v18)*(320/1230)) 41 2.305v 70 v3+((v4-v3)*(380/1230)) 41 2.272v 80 v18+((v17-v18)*(400/1230)) 42 2.324v 70 v3+((v4-v3)*(450/1230)) 42 2.259v 60 v18+((v17-v18)*(460/1230)) 43 2.342v 70 v3+((v4-v3)*(520/1230)) 43 2.241v 80 v18+((v17-v18)*(540/1230)) http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 37 of 60 44 2.839v 70 v3+((v4-v3)*(590/1230)) 44 2.226v 70 v18+((v17-v18)*(610/1230)) 45 2.856v 70 v3+((v4-v3)*(660/1230)) 45 2.211v 70 v18+((v17-v18)*(680/1230)) 46 2.872v 70 v3+((v4-v3)*(730/1230)) 46 2.198v 60 v18+((v17-v18)*(740/1230)) 47 2.889v 70 v3+((v4-v3)*(800/1230)) 47 2.182v 70 v18+((v17-v18)*(810/1230)) 48 2.903v 60 v3+((v4-v3)*(860/1230)) 48 2.169v 60 v18+((v17-v18)*(870/1230)) 49 2.919v 70 v3+((v4-v3)*(930/1230)) 49 2.154v 70 v18+((v17-v18)*(940/1230)) 50 2.933v 60 v3+((v4-v3)*(990/1230)) 50 2.140v 60 v18+((v17-v18)*(1000/1230)) 51 2.948v 60 v3+((v4-v3)*(1050/1230)) 5 1 2.127v 60 v18+((v17-v18)*(1060/1230)) 52 2.962v 60 v3+((v4-v3)*(1110/1230)) 5 2 2.116v 50 v18+((v17-v18)*(1110/1230)) 53 2.976v 60 v3+((v4-v3)*(1170/1230)) 5 3 2.103v 60 v18+((v17-v18)*(1170/1230)) 54 2.990v 60 v4 54 2.090v 60 v17 55 3.003v 60 v4+((v5-v4)*(60/1000)) 55 2.077v 60 v17+((v16-v17)*(60/940)) 56 3.016v 60 v4+((v5-v4)*(120/1000)) 56 2.067v 50 v17+((v16-v17)*(110/940)) 57 3.030v 60 v4+((v5-v4)*(180/1000)) 57 2.054v 60 v17+((v16-v17)*(170/940)) 58 3.041v 50 v4+((v5-v4)*(230/1000)) 58 2.043v 50 v17+((v16-v17)*(220/940)) 59 3.054v 60 v4+((v5-v4)*(290/1000)) 59 2.030v 60 v17+((v16-v17)*(280/940)) 60 3.065v 50 v4+((v5-v4)*(340/1000)) 60 2.020v 50 v17+((v16-v17)*(330/940)) 61 3.078v 60 v4+((v5-v4)*(400/1000)) 61 2.007v 60 v17+((v16-v17)*(390/940)) 62 3.089v 50 v4+((v5-v4)*(450/1000)) 62 1.996v 50 v17+((v16-v17)*(440/940)) 63 3.102v 60 v4+((v5-v4)*(510/1000)) 63 1.986v 50 v17+((v16-v17)*(490/940)) 64 3.113v 50 v4+((v5-v4)*(560/1000)) 64 1.975v 50 v17+((v16-v17)*(540/940)) 65 3.126v 60 v4+((v5-v4)*(620/1000)) 65 1.964v 50 v17+((v16-v17)*(590/940)) 66 3.137v 50 v4+((v5-v4)*(670/1000)) 66 1.954v 50 v17+((v16-v17)*(640/940)) 67 3.151v 60 v4+((v5-v4)*(730/1000)) 67 1.943v 50 v17+((v16-v17)*(690/940)) 68 3.162v 50 v4+((v5-v4)*(780/1000)) 68 1.933v 50 v17+((v16-v17)*(740/940)) 69 3.175v 60 v4+((v5-v4)*(840/1000)) 69 1.922v 50 v17+((v16-v17)*(790/940)) 70 3.186v 50 v4+((v5-v4)*(890/1000)) 70 1.911v 50 v17+((v16-v17)*(840/940)) 71 3.199v 60 v4+((v5-v4)*(950/1000)) 71 1.901v 50 v17+((v16-v17)*(890/940)) 72 3.210v 50 v5 72 1.890v 50 v16 73 3.220v 50 v5+((v6-v5)*(50/980)) 73 1.879v 50 v16+((v15-v16)*(50/810)) 74 3.230v 50 v5+((v6-v5)*(100/980)) 74 1.870v 40 v16+((v15-v16)*(90/810)) 75 3.241v 50 v5+((v6-v5)*(150/980)) 75 1.859v 50 v16+((v15-v16)*(140/810)) 76 3.253v 60 v5+((v6-v5)*(210/980)) 76 1.850v 40 v16+((v15-v16)*(180/810)) 77 3.263v 50 v5+((v6-v5)*(260/980)) 77 1.839v 50 v16+((v15-v16)*(230/810)) 78 3.275v 60 v5+((v6-v5)*(320/980)) 78 1.830v 40 v16+((v15-v16)*(270/810)) 79 3.286v 50 v5+((v6-v5)*(370/980)) 79 1.819v 50 v16+((v15-v16)*(320/810)) 80 3.298v 60 v5+((v6-v5)*(430/980)) 80 1.810v 40 v16+((v15-v16)*(360/810)) 81 3.308v 50 v5+((v6-v5)*(480/980)) 81 1.799v 50 v16+((v15-v16)*(410/810)) 82 3.320v 60 v5+((v6-v5)*(540/980)) 82 1.790v 40 v16+((v15-v16)*(450/810)) 83 3.330v 50 v5+((v6-v5)*(590/980)) 83 1.779v 50 v16+((v15-v16)*(500/810)) 84 3.343v 60 v5+((v6-v5)*(650/980)) 84 1.770v 40 v16+((v15-v16)*(540/810)) 85 3.353v 50 v5+((v6-v5)*(700/980)) 85 1.759v 50 v16+((v15-v16)*(590/810)) 86 3.365v 60 v5+((v6-v5)*(760/980)) 86 1.750v 40 v16+((v15-v16)*(630/810)) 87 3.375v 50 v5+((v6-v5)*(810/980)) 87 1.739v 50 v16+((v15-v16)*(680/810)) 88 3.388v 60 v5+((v6-v5)*(870/980)) 88 1.730v 40 v16+((v15-v16)*(720/810)) 89 3.398v 50 v5+((v6-v5)*(920/980)) 89 1.721v 40 v16+((v15-v16)*(760/810)) http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 38 of 60 90 3.410v 60 v6 90 1.710v 50 v15 91 3.419v 50 v6+((v7-v6)*(50/1090)) 91 1.701v 40 v15+((v14-v15)*(40/830)) 92 3.430v 60 v6+((v7-v6)*(110/1090)) 92 1.690v 50 v15+((v14-v15)*(90/830)) 93 3.441v 60 v6+((v7-v6)*(170/1090)) 93 1.682v 40 v15+((v14-v15)*(130/830)) 94 3.452v 60 v6+((v7-v6)*(230/1090)) 94 1.671v 50 v15+((v14-v15)*(180/830)) 95 3.463v 60 v6+((v7-v6)*(290/1090)) 95 1.662v 40 v15+((v14-v15)*(220/830)) 96 3.474v 60 v6+((v7-v6)*(350/1090)) 96 1.651v 50 v15+((v14-v15)*(270/830)) 97 3.485v 60 v6+((v7-v6)*(410/1090)) 97 1.643v 40 v15+((v14-v15)*(310/830)) 98 3.496v 60 v6+((v7-v6)*(470/1090)) 98 1.630v 60 v15+((v14-v15)*(370/830)) 99 3.507v 60 v6+((v7-v6)*(530/1090)) 99 1.621v 40 v15+((v14-v15)*(410/830)) 100 3.520v 70 v6+((v7-v6)*(600/1090)) 100 1.608v 60 v15+((v14-v15)*(470/830)) 101 3.531v 60 v6+((v7-v6)*(660/1090)) 101 1.599v 40 v15+((v14-v15)*(510/830)) 102 3.544v 70 v6+((v7-v6)*(730/1090)) 102 1.586v 60 v15+((v14-v15)*(570/830)) 103 3.557v 70 v6+((v7-v6)*(800/1090)) 103 1.578v 40 v15+((v14-v15)*(610/830)) 104 3.570v 70 v6+((v7-v6)*(870/1090)) 104 1.565v 60 v15+((v14-v15)*(670/830)) 105 3.582v 70 v6+((v7-v6)*(940/1090)) 105 1.554v 50 v15+((v14-v15)*(720/830)) 106 3.595v 70 v6+((v7-v6)*(1010/1090)) 106 1.541v 60 v15+((v14-v15)*(780/830)) 107 3.610v 80 v7 107 1.530v 50 v14 108 3.622v 70 v7+((v8-v7)*(70/1150)) 108 1.517v 60 v14+((v13-v14)*(60/820)) 109 3.636v 80 v7+((v8-v7)*(150/1150)) 109 1.506v 50 v14+((v13-v14)*(110/820)) 110 3.650v 80 v7+((v8-v7)*(230/1150)) 110 1.493v 60 v14+((v13-v14)*(170/820)) 111 3.664v 80 v7+((v8-v7)*(310/1150)) 111 1.480v 60 v14+((v13-v14)*(230/820)) 112 3.678v 80 v7+((v8-v7)*(390/1150)) 112 1.466v 60 v14+((v13-v14)*(290/820)) 113 3.693v 90 v7+((v8-v7)*(480/1150)) 113 1.453v 60 v14+((v13-v14)*(350/820)) 114 3.709v 90 v7+((v8-v7)*(570/1150)) 114 1.438v 70 v14+((v13-v14)*(420/820)) 115 3.727v 100 v7+((v8-v7)*(670/1150)) 115 1.422v 70 v14+((v13-v14)*(490/820)) 116 3.744v 100 v7+((v8-v7)*(770/1150)) 116 1.405v 80 v14+((v13-v14)*(570/820)) 117 3.761v 100 v7+((v8-v7)*(870/1150)) 117 1.390v 70 v14+((v13-v14)*(640/820)) 118 3.786v 140 v7+((v8-v7)*(1010/1150)) 118 1.370v 90 v14+((v13-v14)*(730/820)) 119 3.810v 140 v8 119 1.350v 90 v13 120 3.835v 150 v8+((v9-v8)*(150/1640)) 120 1.331v 90 v13+((v12-v13)*(90/1120)) 121 3.866v 190 v8+((v9-v8)*(340/1640)) 121 1.301v 140 v13+((v12-v13)*(230/1120)) 122 3.897v 190 v8+((v9-v8)*(530/1640)) 122 1.275v 120 v13+((v12-v13)*(350/1120)) 123 3.945v 290 v8+((v9-v8)*(820/1640)) 123 1.230v 210 v13+((v12-v13)*(560/1120)) 124 3.993v 290 v8+((v9-v8)*(1110/1640)) 124 1.185v 210 v13+((v12-v13)*(770/1120)) 125 4.080v 530 v9 125 1.110v 350 v12 126 4.285v 840 v9+((v10-v9)*(840/2740)) 126 0.980v 600 v12+((v11-v12)*(600/3090)) 127 4.750v 1900 v10 127 0.440v 2490 v11 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 39 of 60 11. wire resistance for each pin the recommended wiring resistance values are shown below. the wiring resistance values affect the current capacity of the power supply, so be sure to desi gn using values that do not exceed those recommended. pin name wiring resistance value(ohm) pin name wiring resistance value(ohm) vdd <10 hsd <50 pvdd <3 vsd <50 gnd <10 dclk <50 agnd <10 den <50 pgnd <3 dr0~dr7 <50 vddio <10 dg0~dg7 <50 vpp_otp <10 db0~db7 <50 vcc <10 csb <50 avdd <10 sda <50 vint1 <5 scl <50 vint2,3 <10 stb <1000 c1ap/m <5 grb <1000 c1bp/m <5 hvdsl <1000 c1cp/m <5 updn <1000 c2p/m <10 shlr <1000 c3p/m <10 pinctl <1000 c4p/m <10 psel <1000 c5p/m <10 cpsel <1000 vcom <5 ext_pwr <1000 vcomh <10 clkpol <1000 vcoml <10 vsdpol <1000 vgh <10 hsdpol <1000 vgl <10 fpol <1000 drv <20 dithb <1000 fb <50 shdb <1000 pwm_out <50 lhl <1000 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 40 of 60 12. dc characteristic 12.1. absolute maximum rating logic supply voltage, vddio -0.5 to +5v analog supply voltage, avdd -0.3 to +7.0v vgl -16 to 0.3v vgh~vgl -0.3 to 35v operating ambient -20 to 85 temperature, ta storage temperature, tstr -55 to+125 stresses above those listed under "absolute maximu m ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of th is device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied and exposed to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating range (gnd=agnd=pgnd=0v, ta= -20 to +85 ) parameters symbol min. typ. max. unit conditions digital supply voltage vdd 2.7 3.3 3.6 v charge pump supply voltage pvdd 2.7 3.3 3.6 v digital interface supple voltage vddio 1.8 - vdd v digital input voltage din 0 - vddio v otp supply voltage vpp_otp - 6 - v vcom ac voltage vcomh - vcoml 2.96 - 6.2 v http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 41 of 60 12.2. dc electrical characteristics (vddio=vdd=2.7 to 3.6v, gnd= agnd=pgnd=0v, ta= -20 to 85 ) parameters symbol min. typ. max. unit conditions digital block circuit low level input voltage vil gnd - 0.3xvddio v digital input pins high level input voltage vih 0.7xvddio - vddio v digital input pins input leakage current ii - - 1 ua digital input pins pull-high/low impedance rin - 200k - ohm digital control input pins vddio=3.3v high level output voltage voh vddio-0.4 - - v digital input pins ioh=400ua low level output voltage vol gnd - gnd+0.4 v digital output pins iol=-400ua digital stand-by current idst - tbd tbd ua output are high-z, all pins are default digital operating current icc - tbd - ma dclk=9mhz, fld=17.28khz (@ 24bit rgb mode), no load analog block circuit analog supply voltage avdd - 5.2 5.6 v gamma reference voltage vdda - 5 - v step-up circuit 1 output vo ltage vint1 5.8 - - v vcomh output level vcomh 2.46 5 v by vcomh[6:0] setting vcoml output level vcoml -3 -0.46 v by vcoml[6:0] setting; vcoml>vint3 feed back voltage for pwm vfb 0.25 0.6 0. 8 v dc-dc operating. base drive current for pwm idrv - 20 - ma vdd=3.3v - 20 35 mv vo=0.1v ~ 0.5v & avdd-0.5 ~ avdd-0.1 voltage deviation of outputs vvd - 15 20 mv vo=0.5v ~ avdd-0.5v dynamic range of ouput vdr 0.1 - avdd-0.1 v s1 to s720 low-level output current of vcom iolc - tbd - ma vcomh=4v, vcoml=-1v vcom output=-1v v.s. -0.1v high-level output current of vcom iohc - tbd - ma vcomh=4v, vcoml=-1v vcom output=4v v.s. 3.1v source low-level output current iols tbd - - ua s1 to s720; vo=0.1 v.s. 1v source high-level output current iohs tbd - - ua s1 to s720; vo=4.9 v.s 4.0 gate low-level output current iolg -200 - - ua g1 to g544; vo=vgl v.s. vgl+0.5 gate high-level output current iohg 200 - - ua g1 to g544; vo=vgh v.s. vgh-0.5 analog stand-by current iast - - 100 ua stb=?l?, all function are shutdown analog operating current idd - tbd - ma dclk=9mhz, fld=17.28khz (@ 24bit rgb mode), no load http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 42 of 60 13. ac characteristic 13.1. input signal characteristics ac electrical characteristics (vddio=vdd=2.7 to 3.6v, gnd=0v, ta=-20 to +85 ) parameters symbol min. typ. max. unit conditions system operation timing vdd power source slew time tpor - - 20 ms from 0v to 99% vdd grb pulse width trstw 10 50 - us r=10kohm, c=1uf input output timing dclk clock time tclk 33.3 - - ns dclk=30mhz dclk clock low period tcwl 40 - 60 % dclk clock high period tcwh 40 - 60 % clock rising time trck 9 - - ns clock falling time tfck 9 - - ns hsd width thwh 1 - - dclk hsd period time th 55 60 65 us hsd setup time thsu 12 - - ns hsd hold time thhd 12 - - ns vsd width tvwh 1 - - th vsd setup time tvsu 12 - - ns vsd hold time tvhd 12 - - ns data setup time tdasu 12 - - ns data hold time tdahd 12 - - ns de setup time tdesu 12 - - ns de hold time tdehd 12 - - ns source output setting time tsst - - tbd us 10% to 90% cl=60pf, rl=2kohm gate output setting time tgst - 500 1000 ns 10% to 90%, cl=60pf vcom output setting time tcst - - tbd us 10% to 90%, cl=40nf, rl=50ohm time from vsd to 1st line data input tvs 3 8 31 th hv mode by hdl[4:0] setting 3-wire serial communication ac timing serial clock tsck 200 - - ns for scl pin scl pulse low period tckl 40 - 60 % scl pulse low period tckh 40 - 60 % serial data setup time tisu 50 - - ns serial data hold time tihd 50 - - ns serial clock high/low tssw 50 - - ns csb to vsd tcv 1 us csb distinguish time tcd 400 - - ns csb input setup time tcsu 50 - - ns csb input hold time tchd 50 - - ns http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 43 of 60 14. waveform 14.1. timing chart 14.1.1. clock and data input waveforms 1st data 2nd data last data data de dclk tclk tcwh tcwl 70% 70% 30% 10% 90% 90% 10% trck tfck 70% 30% tdehd tdesu tdahd tdasu tvwh tclk tcwh tcwl 70% 70% 70% 30% 30% 30% 30% thsu thhd tvsu tvhd 30% 30% thwh th 70% dclk vsync hsync http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 44 of 60 14.1.2. data input format tvwh vsd hsd de tvbp tvd tvfp vertical input timing tv 1 hsync dclk 23 475 476 477 478 480 479 4 5 6 data thwh 1 23 475 476 477 478 480 479 4 5 6 data h back porch(thbp) h front porch(thfb) active area(thd) total area (th) (hv mode) (de mode) serial 8-bit rgb mode data format parameters symbol min. typ. max. unit conditions dclk frequency fclk 24 27 30 mhz dclk cycle time tclk 83 110 200 ns dclk pulse duty tcwh 40 50 60 % time from hsd to source output thso - 13 - dclk time from hsd to gate output thgo - 27 - dclk time from hsd to gate output off thgz - 3 - dclk time from hsd to vcom thvc - 12 - dclk http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 45 of 60 hsd dclk r0 r1 rn-1 rn r2 r3 dr[7:0] thwh (hv mode) (de mode) g0 g1 gn-1 gn g2 g3 dg[7:0] b0 b1 bn-1 bn b2 b3 db[7:0] dclk r0 r1 rn-1 rn r2 r3 dr[7:0] g0 g1 gn-1 gn g2 g3 dg[7:0] b0 b1 bn-1 bn b2 b3 db[7:0] de h back porch(thbp) h front porch(thfb) active area(thd) total area(th) parallel rgb m ode data format parallel rgb input timign table value parameter symbol min. typ. max. unit dclk frequency fclk 5 9 12 mhz vsd period time tv 277 288 400 h vsd display area tvd 272 h vsd back porch tvb 3 8 31 h vsd front porch tvfp 2 8 93 h hsd period time th 520 525 800 dclk hsd display area thd 480 dclk hsd back porch thbp 36 40 255 dclk hsd front porch thfp 4 5 65 dclk serial rgb input timign table value parameter symbol min. typ. max. unit dclk frequency fclk - 27 - mhz vsd period time tv 277 288 400 h vsd display area tvd 272 h vsd back porch tvb 3 8 31 h vsd front porch tvfp 2 8 93 h hsd period time th - 1575 - dclk hsd display area thd 1440 dclk http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 46 of 60 hsd back porch thbp - 120 - dclk hsd front porch thfp - 15 - dclk 14.1.3. 3-wire timing diagram 14.1.4. output timing diagram hsync source output gate output @n line gate output @n+1 line vcom 30 % ?th thso tsst 90 % 10 % thso tsst 90 % 10 % thgo 90 % 10 % tgst thgz 90 % 10 % tgst thgo 90 % 10 % tgst thgz 90 % 10 % tgst 90 % 10 % tcst thvc thvc 90 % 10 % tcst vcc gnd avdd agnd vgh vgl vgh vgl vcomh vcoml http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 47 of 60 15. pin assignment (ic face view) dum shielding1 tp0 tp1 tp2 tp3 tp4 tp5 tp6 tp7 tp8 tp9 tp10 dswp rbswp tm2 tm3 tb2 tb3 lhl ext _pwr shdb fpol dithb vsdpol hsdpol clkpol tb0 tb1 tcsw0 tcsw1 vpp_otp shielding2 com1_l shielding3 vcomh vcoml vcom dum shielding4 fb shielding5 drv gnd vcc vddio vdd vsd hsd dclk den psel csb/dcmp_en sda/cabc_mode0 scl/cac_mode1 stb grb hvdsl updn shlr pinctl cpsel shielding6 dr0 dr1 dr2 dr3 dr4 dr5 dr6 dr7 dg0 dg1 dg2 dg3 dg4 dg5 dg6 dg7 db0 db1 db2 db3 db4 db5 db6 db7 shielding7 avdd agnd shielding8 vint3 c5m c5p vint1 pgnd com2_l c1ap c1am c1bp c1bm c1cp c1cm pvdd c2p c2m vint2 shielding9 c3p c3m vgh c4p c4m vgl shieling10 dum (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (3) (1) (2) (1) (3) (3) (6) (3) (1) (1) (1) (2) (3) (3) (3) (3) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (6) (6) (1) (4) (3) (3) (6) (8) (2) (3) (3) (3) (3) (3) (3) (8) (2) (2) (3) (1) (2) (2) (3) (2) (2) (3) (1) (1) dum g1 g3 g5 (1) (1) (1) (1) g539 g541 g543 com1_r com1_r com1_r com1_r com1_r s720 s719 s718 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) s363 s362 s361 dcmp dcmp dcmp dcmp dcmp dcmp dcmp dcmp s360 s359 s358 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) s3 s2 s1 com2_r com2_r com2_r com2_r com2_r g544 g542 g540 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) g6 g4 g2 dum (1) (1) (1) (1) bump view ili6480 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 48 of 60 15.1. pad location pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 1 dum -10941.5 -256 51 dum -5441.5 -256 101 dg6 58.5 -256 2 shielding1 -10831.5 -256 52 dum -5331.5 -256 102 dg7 168.5 -256 3 tp0 -10721.5 -256 53 dum -5221.5 -256 103 db0 278.5 -256 4 tp1 -10611.5 -256 54 shielding4 -5111.5 -256 104 db1 388.5 -256 5 tp2 -10501.5 -256 55 fb -5001.5 -256 105 db2 498.5 -256 6 tp3 -10391.5 -256 56 shielding5 -4891.5 -256 106 db3 608.5 -256 7 tp4 -10281.5 -256 57 drv -4781.5 -256 107 db4 718.5 -256 8 tp5 -10171.5 -256 58 drv -4671.5 -256 108 db5 828.5 -256 9 tp6 -10061.5 -256 59 gnd -4561.5 -256 109 db6 938.5 -256 10 tp7 -9951.5 -256 60 gnd -4451.5 -256 110 db7 1048.5 -256 11 tp8 -9841.5 -256 61 gnd -4341.5 -256 111 shielding7 1158.5 -256 12 tp9 -9731.5 -256 62 vcc -4231.5 -256 112 avdd 1268.5 -256 13 tp10 -9621.5 -256 63 vcc -4121.5 -256 113 avdd 1378.5 -256 14 dswp -9511.5 -256 64 vcc -4011.5 -256 114 avdd 1488.5 -256 15 rbswp -9401.5 -256 65 vddio -3901.5 -256 115 avdd 1598.5 -256 16 tm2 -9291.5 -256 66 vddio -3791.5 -256 116 avdd 1708.5 -256 17 tm3 -9181.5 -256 67 vddio -3681.5 -256 117 avdd 1818.5 -256 18 tb2 -9071.5 -256 68 vdd -3571.5 -256 118 agnd 1928.5 -256 19 tb3 -8961.5 -256 69 vdd -3461.5 -256 119 agnd 2038.5 -256 20 lhl -8851.5 -256 70 vdd -3351.5 -256 120 agnd 2148.5 -256 21 ext_pwr -8741.5 -256 71 vsd -3241.5 -256 121 agnd 2258.5 -256 22 shdb -8631.5 -256 72 hsd -3131.5 -256 122 agnd 2368.5 -256 23 fpol -8521.5 -256 73 dclk -3021.5 -256 123 agnd 2478.5 -256 24 dithb -8411.5 -256 74 den -2911.5 -256 124 shielding8 2588.5 -256 25 vsdpol -8301.5 -256 75 psel -2801.5 -256 125 vint3 2698.5 -256 26 hsdpol -8191.5 -256 76 csb/reserved -2691.5 -256 126 vint3 2808.5 -256 27 clkpol -8081.5 -256 77 sda/cabc_mode0 -2581.5 -256 127 vint3 2918.5 -256 28 tb0 (pwm_out) -7971.5 -256 78 scl/cabc_mode1 -2471.5 -256 128 vint3 3028.5 -256 29 tb1 -7861.5 -256 79 stb -2361.5 -256 129 c5m 3138.5 -256 30 tcsw0 -7751.5 -256 80 grb -2251.5 -256 130 c5m 3248.5 -256 31 tcsw1 -7641.5 -256 81 hvdsl -2141.5 -256 131 c5m 3358.5 -256 32 vpp_otp -7531.5 -256 82 updn -2031.5 -256 132 c5p 3468.5 -256 33 vpp_otp -7421.5 -256 83 shlr -1921.5 -256 133 c5p 3578.5 -256 34 vpp_otp -7311.5 -256 84 pinctl -1811.5 -256 134 c5p 3688.5 -256 35 shielding2 -7201.5 -256 85 cpsel -1701.5 -256 135 vint1 3798.5 -256 36 com1_l -7091.5 -256 86 shielding6 -1591.5 -256 136 vint1 3908.5 -256 37 com1_l -6981.5 -256 87 dr0 -1481.5 -256 137 vint1 4018.5 -256 38 shielding3 -6871.5 -256 88 dr1 -1371.5 -256 138 vint1 4128.5 -256 39 vcomh -6761.5 -256 89 dr2 -1261.5 -256 139 vint1 4238.5 -256 40 vcomh -6651.5 -256 90 dr3 -1151.5 -256 140 vint1 4348.5 -256 41 vcomh -6541.5 -256 91 dr4 -1041.5 -256 141 pgnd 4458.5 -256 42 vcoml -6431.5 -256 92 dr5 -931.5 -256 142 pgnd 4568.5 -256 43 vcoml -6321.5 -256 93 dr6 -821.5 -256 143 pgnd 4678.5 -256 44 vcoml -6211.5 -256 94 dr7 -711.5 -256 144 pgnd 4788.5 -256 45 vcom -6101.5 -256 95 dg0 -601.5 -256 145 pgnd 4898.5 -256 46 vcom -5991.5 -256 96 dg1 -491.5 -256 146 pgnd 5008.5 -256 47 vcom -5881.5 -256 97 dg2 -381.5 -256 147 pgnd 5118.5 -256 48 vcom -5771.5 -256 98 dg3 -271.5 -256 148 pgnd 5228.5 -256 49 vcom -5661.5 -256 99 dg4 -161.5 -256 149 com2_l 5338.5 -256 50 vcom -5551.5 -256 100 dg5 -51.5 -256 150 com2_l 5448.5 -256 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 49 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 151 c1ap 5558.5 -256 201 dum 11135 261 251 g100 10268 261 152 c1ap 5668.5 -256 202 g2 11101 121 252 g102 10251 121 153 c1ap 5778.5 -256 203 g4 11084 261 253 g104 10234 261 154 c1am 5888.5 -256 204 g6 11067 121 254 g106 10217 121 155 c1am 5998.5 -256 205 g8 11050 261 255 g108 10200 261 156 c1am 6108.5 -256 206 g10 11033 121 256 g110 10183 121 157 c1bp 6218.5 -256 207 g12 11016 261 257 g112 10166 261 158 c1bp 6328.5 -256 208 g14 10999 121 258 g114 10149 121 159 c1bp 6438.5 -256 209 g16 10982 261 259 g116 10132 261 160 c1bm 6548.5 -256 210 g18 10965 121 260 g118 10115 121 161 c1bm 6658.5 -256 211 g20 10948 261 261 g120 10098 261 162 c1bm 6768.5 -256 212 g22 10931 121 262 g122 10081 121 163 c1cp 6878.5 -256 213 g24 10914 261 263 g124 10064 261 164 c1cp 6988.5 -256 214 g26 10897 121 264 g126 10047 121 165 c1cp 7098.5 -256 215 g28 10880 261 265 g128 10030 261 166 c1cm 7208.5 -256 216 g30 10863 121 266 g130 10013 121 167 c1cm 7318.5 -256 217 g32 10846 261 267 g132 9996 261 168 c1cm 7428.5 -256 218 g34 10829 121 268 g134 9979 121 169 pvdd 7538.5 -256 219 g36 10812 261 269 g136 9962 261 170 pvdd 7648.5 -256 220 g38 10795 121 270 g138 9945 121 171 pvdd 7758.5 -256 221 g40 10778 261 271 g140 9928 261 172 pvdd 7868.5 -256 222 g42 10761 121 272 g142 9911 121 173 pvdd 7978.5 -256 223 g44 10744 261 273 g144 9894 261 174 pvdd 8088.5 -256 224 g46 10727 121 274 g146 9877 121 175 pvdd 8198.5 -256 225 g48 10710 261 275 g148 9860 261 176 pvdd 8308.5 -256 226 g50 10693 121 276 g150 9843 121 177 c2p 8418.5 -256 227 g52 10676 261 277 g152 9826 261 178 c2p 8528.5 -256 228 g54 10659 121 278 g154 9809 121 179 c2m 8638.5 -256 229 g56 10642 261 279 g156 9792 261 180 c2m 8748.5 -256 230 g58 10625 121 280 g158 9775 121 181 vint2 8858.5 -256 231 g60 10608 261 281 g160 9758 261 182 vint2 8968.5 -256 232 g62 10591 121 282 g162 9741 121 183 vint2 9078.5 -256 233 g64 10574 261 283 g164 9724 261 184 shielding9 9188.5 -256 234 g66 10557 121 284 g166 9707 121 185 c3p 9298.5 -256 235 g68 10540 261 285 g168 9690 261 186 c3p 9408.5 -256 236 g70 10523 121 286 g170 9673 121 187 c3m 9518.5 -256 237 g72 10506 261 287 g172 9656 261 188 c3m 9628.5 -256 238 g74 10489 121 288 g174 9639 121 189 vgh 9738.5 -256 239 g76 10472 261 289 g176 9622 261 190 vgh 9848.5 -256 240 g78 10455 121 290 g178 9605 121 191 vgh 9958.5 -256 241 g80 10438 261 291 g180 9588 261 192 c4p 10068.5 -256 242 g82 10421 121 292 g182 9571 121 193 c4p 10178.5 -256 243 g84 10404 261 293 g184 9554 261 194 c4m 10288.5 -256 244 g86 10387 121 294 g186 9537 121 195 c4m 10398.5 -256 245 g88 10370 261 295 g188 9520 261 196 vgl 10508.5 -256 246 g90 10353 121 296 g190 9503 121 197 vgl 10618.5 -256 247 g92 10336 261 297 g192 9486 261 198 vgl 10728.5 -256 248 g94 10319 121 298 g194 9469 121 199 shielding10 10838.5 -256 249 g96 10302 261 299 g196 9452 261 200 dum 10948.5 -256 250 g98 10285 121 300 g198 9435 121 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 50 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 301 g200 9418 261 351 g300 8568 261 401 g400 7718 261 302 g202 9401 121 352 g302 8551 121 402 g402 7701 121 303 g204 9384 261 353 g304 8534 261 403 g404 7684 261 304 g206 9367 121 354 g306 8517 121 404 g406 7667 121 305 g208 9350 261 355 g308 8500 261 405 g408 7650 261 306 g210 9333 121 356 g310 8483 121 406 g410 7633 121 307 g212 9316 261 357 g312 8466 261 407 g412 7616 261 308 g214 9299 121 358 g314 8449 121 408 g414 7599 121 309 g216 9282 261 359 g316 8432 261 409 g416 7582 261 310 g218 9265 121 360 g318 8415 121 410 g418 7565 121 311 g220 9248 261 361 g320 8398 261 411 g420 7548 261 312 g222 9231 121 362 g322 8381 121 412 g422 7531 121 313 g224 9214 261 363 g324 8364 261 413 g424 7514 261 314 g226 9197 121 364 g326 8347 121 414 g426 7497 121 315 g228 9180 261 365 g328 8330 261 415 g428 7480 261 316 g230 9163 121 366 g330 8313 121 416 g430 7463 121 317 g232 9146 261 367 g332 8296 261 417 g432 7446 261 318 g234 9129 121 368 g334 8279 121 418 g434 7429 121 319 g236 9112 261 369 g336 8262 261 419 g436 7412 261 320 g238 9095 121 370 g338 8245 121 420 g438 7395 121 321 g240 9078 261 371 g340 8228 261 421 g440 7378 261 322 g242 9061 121 372 g342 8211 121 422 g442 7361 121 323 g244 9044 261 373 g344 8194 261 423 g444 7344 261 324 g246 9027 121 374 g346 8177 121 424 g446 7327 121 325 g248 9010 261 375 g348 8160 261 425 g448 7310 261 326 g250 8993 121 376 g350 8143 121 426 g450 7293 121 327 g252 8976 261 377 g352 8126 261 427 g452 7276 261 328 g254 8959 121 378 g354 8109 121 428 g454 7259 121 329 g256 8942 261 379 g356 8092 261 429 g456 7242 261 330 g258 8925 121 380 g358 8075 121 430 g458 7225 121 331 g260 8908 261 381 g360 8058 261 431 g460 7208 261 332 g262 8891 121 382 g362 8041 121 432 g462 7191 121 333 g264 8874 261 383 g364 8024 261 433 g464 7174 261 334 g266 8857 121 384 g366 8007 121 434 g466 7157 121 335 g268 8840 261 385 g368 7990 261 435 g468 7140 261 336 g270 8823 121 386 g370 7973 121 436 g470 7123 121 337 g272 8806 261 387 g372 7956 261 437 g472 7106 261 338 g274 8789 121 388 g374 7939 121 438 g474 7089 121 339 g276 8772 261 389 g376 7922 261 439 g476 7072 261 340 g278 8755 121 390 g378 7905 121 440 g478 7055 121 341 g280 8738 261 391 g380 7888 261 441 g480 7038 261 342 g282 8721 121 392 g382 7871 121 442 g482 7021 121 343 g284 8704 261 393 g384 7854 261 443 g484 7004 261 344 g286 8687 121 394 g386 7837 121 444 g486 6987 121 345 g288 8670 261 395 g388 7820 261 445 g488 6970 261 346 g290 8653 121 396 g390 7803 121 446 g490 6953 121 347 g292 8636 261 397 g392 7786 261 447 g492 6936 261 348 g294 8619 121 398 g394 7769 121 448 g494 6919 121 349 g296 8602 261 399 g396 7752 261 449 g496 6902 261 350 g298 8585 121 400 g398 7735 121 450 g498 6885 121 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 51 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 451 g500 6868 261 501 s23 5899 121 551 s73 5049 121 452 g502 6851 121 502 s24 5882 261 552 s74 5032 261 453 g504 6834 261 503 s25 5865 121 553 s75 5015 121 454 g506 6817 121 504 s26 5848 261 554 s76 4998 261 455 g508 6800 261 505 s27 5831 121 555 s77 4981 121 456 g510 6783 121 506 s28 5814 261 556 s78 4964 261 457 g512 6766 261 507 s29 5797 121 557 s79 4947 121 458 g514 6749 121 508 s30 5780 261 558 s80 4930 261 459 g516 6732 261 509 s31 5763 121 559 s81 4913 121 460 g518 6715 121 510 s32 5746 261 560 s82 4896 261 461 g520 6698 261 511 s33 5729 121 561 s83 4879 121 462 g522 6681 121 512 s34 5712 261 562 s84 4862 261 463 g524 6664 261 513 s35 5695 121 563 s85 4845 121 464 g526 6647 121 514 s36 5678 261 564 s86 4828 261 465 g528 6630 261 515 s37 5661 121 565 s87 4811 121 466 g530 6613 121 516 s38 5644 261 566 s88 4794 261 467 g532 6596 261 517 s39 5627 121 567 s89 4777 121 468 g534 6579 121 518 s40 5610 261 568 s90 4760 261 469 g536 6562 261 519 s41 5593 121 569 s91 4743 121 470 g538 6545 121 520 s42 5576 261 570 s92 4726 261 471 g540 6528 261 521 s43 5559 121 571 s93 4709 121 472 g542 6511 121 522 s44 5542 261 572 s94 4692 261 473 g544 6494 261 523 s45 5525 121 573 s95 4675 121 474 com2_r 6443 261 524 s46 5508 261 574 s96 4658 261 475 com2_r 6409 261 525 s47 5491 121 575 s97 4641 121 476 com2_r 6375 261 526 s48 5474 261 576 s98 4624 261 477 com2_r 6341 261 527 s49 5457 121 577 s99 4607 121 478 com2_r 6307 261 528 s50 5440 261 578 s100 4590 261 479 s1 6273 121 529 s51 5423 121 579 s101 4573 121 480 s2 6256 261 530 s52 5406 261 580 s102 4556 261 481 s3 6239 121 531 s53 5389 121 581 s103 4539 121 482 s4 6222 261 532 s54 5372 261 582 s104 4522 261 483 s5 6205 121 533 s55 5355 121 583 s105 4505 121 484 s6 6188 261 534 s56 5338 261 584 s106 4488 261 485 s7 6171 121 535 s57 5321 121 585 s107 4471 121 486 s8 6154 261 536 s58 5304 261 586 s108 4454 261 487 s9 6137 121 537 s59 5287 121 587 s109 4437 121 488 s10 6120 261 538 s60 5270 261 588 s110 4420 261 489 s11 6103 121 539 s61 5253 121 589 s111 4403 121 490 s12 6086 261 540 s62 5236 261 590 s112 4386 261 491 s13 6069 121 541 s63 5219 121 591 s113 4369 121 492 s14 6052 261 542 s64 5202 261 592 s114 4352 261 493 s15 6035 121 543 s65 5185 121 593 s115 4335 121 494 s16 6018 261 544 s66 5168 261 594 s116 4318 261 495 s17 6001 121 545 s67 5151 121 595 s117 4301 121 496 s18 5984 261 546 s68 5134 261 596 s118 4284 261 497 s19 5967 121 547 s69 5117 121 597 s119 4267 121 498 s20 5950 261 548 s70 5100 261 598 s120 4250 261 499 s21 5933 121 549 s71 5083 121 599 s121 4233 121 500 s22 5916 261 550 s72 5066 261 600 s122 4216 261 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 52 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 601 s123 4199 121 651 s173 3349 121 701 s223 2499 121 602 s124 4182 261 652 s174 3332 261 702 s224 2482 261 603 s125 4165 121 653 s175 3315 121 703 s225 2465 121 604 s126 4148 261 654 s176 3298 261 704 s226 2448 261 605 s127 4131 121 655 s177 3281 121 705 s227 2431 121 606 s128 4114 261 656 s178 3264 261 706 s228 2414 261 607 s129 4097 121 657 s179 3247 121 707 s229 2397 121 608 s130 4080 261 658 s180 3230 261 708 s230 2380 261 609 s131 4063 121 659 s181 3213 121 709 s231 2363 121 610 s132 4046 261 660 s182 3196 261 710 s232 2346 261 611 s133 4029 121 661 s183 3179 121 711 s233 2329 121 612 s134 4012 261 662 s184 3162 261 712 s234 2312 261 613 s135 3995 121 663 s185 3145 121 713 s235 2295 121 614 s136 3978 261 664 s186 3128 261 714 s236 2278 261 615 s137 3961 121 665 s187 3111 121 715 s237 2261 121 616 s138 3944 261 666 s188 3094 261 716 s238 2244 261 617 s139 3927 121 667 s189 3077 121 717 s239 2227 121 618 s140 3910 261 668 s190 3060 261 718 s240 2210 261 619 s141 3893 121 669 s191 3043 121 719 s241 2193 121 620 s142 3876 261 670 s192 3026 261 720 s242 2176 261 621 s143 3859 121 671 s193 3009 121 721 s243 2159 121 622 s144 3842 261 672 s194 2992 261 722 s244 2142 261 623 s145 3825 121 673 s195 2975 121 723 s245 2125 121 624 s146 3808 261 674 s196 2958 261 724 s246 2108 261 625 s147 3791 121 675 s197 2941 121 725 s247 2091 121 626 s148 3774 261 676 s198 2924 261 726 s248 2074 261 627 s149 3757 121 677 s199 2907 121 727 s249 2057 121 628 s150 3740 261 678 s200 2890 261 728 s250 2040 261 629 s151 3723 121 679 s201 2873 121 729 s251 2023 121 630 s152 3706 261 680 s202 2856 261 730 s252 2006 261 631 s153 3689 121 681 s203 2839 121 731 s253 1989 121 632 s154 3672 261 682 s204 2822 261 732 s254 1972 261 633 s155 3655 121 683 s205 2805 121 733 s255 1955 121 634 s156 3638 261 684 s206 2788 261 734 s256 1938 261 635 s157 3621 121 685 s207 2771 121 735 s257 1921 121 636 s158 3604 261 686 s208 2754 261 736 s258 1904 261 637 s159 3587 121 687 s209 2737 121 737 s259 1887 121 638 s160 3570 261 688 s210 2720 261 738 s260 1870 261 639 s161 3553 121 689 s211 2703 121 739 s261 1853 121 640 s162 3536 261 690 s212 2686 261 740 s262 1836 261 641 s163 3519 121 691 s213 2669 121 741 s263 1819 121 642 s164 3502 261 692 s214 2652 261 742 s264 1802 261 643 s165 3485 121 693 s215 2635 121 743 s265 1785 121 644 s166 3468 261 694 s216 2618 261 744 s266 1768 261 645 s167 3451 121 695 s217 2601 121 745 s267 1751 121 646 s168 3434 261 696 s218 2584 261 746 s268 1734 261 647 s169 3417 121 697 s219 2567 121 747 s269 1717 121 648 s170 3400 261 698 s220 2550 261 748 s270 1700 261 649 s171 3383 121 699 s221 2533 121 749 s271 1683 121 650 s172 3366 261 700 s222 2516 261 750 s272 1666 261 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 53 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 751 s273 1649 121 801 s323 799 121 851 s365 -238 261 752 s274 1632 261 802 s324 782 261 852 s366 -255 121 753 s275 1615 121 803 s325 765 121 853 s367 -272 261 754 s276 1598 261 804 s326 748 261 854 s368 -289 121 755 s277 1581 121 805 s327 731 121 855 s369 -306 261 756 s278 1564 261 806 s328 714 261 856 s370 -323 121 757 s279 1547 121 807 s329 697 121 857 s371 -340 261 758 s280 1530 261 808 s330 680 261 858 s372 -357 121 759 s281 1513 121 809 s331 663 121 859 s373 -374 261 760 s282 1496 261 810 s332 646 261 860 s374 -391 121 761 s283 1479 121 811 s333 629 121 861 s375 -408 261 762 s284 1462 261 812 s334 612 261 862 s376 -425 121 763 s285 1445 121 813 s335 595 121 863 s377 -442 261 764 s286 1428 261 814 s336 578 261 864 s378 -459 121 765 s287 1411 121 815 s337 561 121 865 s379 -476 261 766 s288 1394 261 816 s338 544 261 866 s380 -493 121 767 s289 1377 121 817 s339 527 121 867 s381 -510 261 768 s290 1360 261 818 s340 510 261 868 s382 -527 121 769 s291 1343 121 819 s341 493 121 869 s383 -544 261 770 s292 1326 261 820 s342 476 261 870 s384 -561 121 771 s293 1309 121 821 s343 459 121 871 s385 -578 261 772 s294 1292 261 822 s344 442 261 872 s386 -595 121 773 s295 1275 121 823 s345 425 121 873 s387 -612 261 774 s296 1258 261 824 s346 408 261 874 s388 -629 121 775 s297 1241 121 825 s347 391 121 875 s389 -646 261 776 s298 1224 261 826 s348 374 261 876 s390 -663 121 777 s299 1207 121 827 s349 357 121 877 s391 -680 261 778 s300 1190 261 828 s350 340 261 878 s392 -697 121 779 s301 1173 121 829 s351 323 121 879 s393 -714 261 780 s302 1156 261 830 s352 306 261 880 s394 -731 121 781 s303 1139 121 831 s353 289 121 881 s395 -748 261 782 s304 1122 261 832 s354 272 261 882 s396 -765 121 783 s305 1105 121 833 s355 255 121 883 s397 -782 261 784 s306 1088 261 834 s356 238 261 884 s398 -799 121 785 s307 1071 121 835 s357 221 121 885 s399 -816 261 786 s308 1054 261 836 s358 204 261 886 s400 -833 121 787 s309 1037 121 837 s359 187 121 887 s401 -850 261 788 s310 1020 261 838 s360 170 261 888 s402 -867 121 789 s311 1003 121 839 dcmp 119 261 889 s403 -884 261 790 s312 986 261 840 dcmp 85 261 890 s404 -901 121 791 s313 969 121 841 dcmp 51 261 891 s405 -918 261 792 s314 952 261 842 dcmp 17 261 892 s406 -935 121 793 s315 935 121 843 dcmp -17 261 893 s407 -952 261 794 s316 918 261 844 dcmp -51 261 894 s408 -969 121 795 s317 901 121 845 dcmp -85 261 895 s409 -986 261 796 s318 884 261 846 dcmp -119 261 896 s410 -1003 121 797 s319 867 121 847 s361 -170 261 897 s411 -1020 261 798 s320 850 261 848 s362 -187 121 898 s412 -1037 121 799 s321 833 121 849 s363 -204 261 899 s413 -1054 261 800 s322 816 261 850 s364 -221 121 900 s414 -1071 121 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 54 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 901 s415 -1088 261 951 s465 -1938 261 1001 s515 -2788 261 902 s416 -1105 121 952 s466 -1955 121 1002 s516 -2805 121 903 s417 -1122 261 953 s467 -1972 261 1003 s517 -2822 261 904 s418 -1139 121 954 s468 -1989 121 1004 s518 -2839 121 905 s419 -1156 261 955 s469 -2006 261 1005 s519 -2856 261 906 s420 -1173 121 956 s470 -2023 121 1006 s520 -2873 121 907 s421 -1190 261 957 s471 -2040 261 1007 s521 -2890 261 908 s422 -1207 121 958 s472 -2057 121 1008 s522 -2907 121 909 s423 -1224 261 959 s473 -2074 261 1009 s523 -2924 261 910 s424 -1241 121 960 s474 -2091 121 1010 s524 -2941 121 911 s425 -1258 261 961 s475 -2108 261 1011 s525 -2958 261 912 s426 -1275 121 962 s476 -2125 121 1012 s526 -2975 121 913 s427 -1292 261 963 s477 -2142 261 1013 s527 -2992 261 914 s428 -1309 121 964 s478 -2159 121 1014 s528 -3009 121 915 s429 -1326 261 965 s479 -2176 261 1015 s529 -3026 261 916 s430 -1343 121 966 s480 -2193 121 1016 s530 -3043 121 917 s431 -1360 261 967 s481 -2210 261 1017 s531 -3060 261 918 s432 -1377 121 968 s482 -2227 121 1018 s532 -3077 121 919 s433 -1394 261 969 s483 -2244 261 1019 s533 -3094 261 920 s434 -1411 121 970 s484 -2261 121 1020 s534 -3111 121 921 s435 -1428 261 971 s485 -2278 261 1021 s535 -3128 261 922 s436 -1445 121 972 s486 -2295 121 1022 s536 -3145 121 923 s437 -1462 261 973 s487 -2312 261 1023 s537 -3162 261 924 s438 -1479 121 974 s488 -2329 121 1024 s538 -3179 121 925 s439 -1496 261 975 s489 -2346 261 1025 s539 -3196 261 926 s440 -1513 121 976 s490 -2363 121 1026 s540 -3213 121 927 s441 -1530 261 977 s491 -2380 261 1027 s541 -3230 261 928 s442 -1547 121 978 s492 -2397 121 1028 s542 -3247 121 929 s443 -1564 261 979 s493 -2414 261 1029 s543 -3264 261 930 s444 -1581 121 980 s494 -2431 121 1030 s544 -3281 121 931 s445 -1598 261 981 s495 -2448 261 1031 s545 -3298 261 932 s446 -1615 121 982 s496 -2465 121 1032 s546 -3315 121 933 s447 -1632 261 983 s497 -2482 261 1033 s547 -3332 261 934 s448 -1649 121 984 s498 -2499 121 1034 s548 -3349 121 935 s449 -1666 261 985 s499 -2516 261 1035 s549 -3366 261 936 s450 -1683 121 986 s500 -2533 121 1036 s550 -3383 121 937 s451 -1700 261 987 s501 -2550 261 1037 s551 -3400 261 938 s452 -1717 121 988 s502 -2567 121 1038 s552 -3417 121 939 s453 -1734 261 989 s503 -2584 261 1039 s553 -3434 261 940 s454 -1751 121 990 s504 -2601 121 1040 s554 -3451 121 941 s455 -1768 261 991 s505 -2618 261 1041 s555 -3468 261 942 s456 -1785 121 992 s506 -2635 121 1042 s556 -3485 121 943 s457 -1802 261 993 s507 -2652 261 1043 s557 -3502 261 944 s458 -1819 121 994 s508 -2669 121 1044 s558 -3519 121 945 s459 -1836 261 995 s509 -2686 261 1045 s559 -3536 261 946 s460 -1853 121 996 s510 -2703 121 1046 s560 -3553 121 947 s461 -1870 261 997 s511 -2720 261 1047 s561 -3570 261 948 s462 -1887 121 998 s512 -2737 121 1048 s562 -3587 121 949 s463 -1904 261 999 s513 -2754 261 1049 s563 -3604 261 950 s464 -1921 121 1000 s514 -2771 121 1050 s564 -3621 121 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 55 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 1051 s565 -3638 261 1101 s615 -4488 261 1151 s665 -5338 261 1052 s566 -3655 121 1102 s616 -4505 121 1152 s666 -5355 121 1053 s567 -3672 261 1103 s617 -4522 261 1153 s667 -5372 261 1054 s568 -3689 121 1104 s618 -4539 121 1154 s668 -5389 121 1055 s569 -3706 261 1105 s619 -4556 261 1155 s669 -5406 261 1056 s570 -3723 121 1106 s620 -4573 121 1156 s670 -5423 121 1057 s571 -3740 261 1107 s621 -4590 261 1157 s671 -5440 261 1058 s572 -3757 121 1108 s622 -4607 121 1158 s672 -5457 121 1059 s573 -3774 261 1109 s623 -4624 261 1159 s673 -5474 261 1060 s574 -3791 121 1110 s624 -4641 121 1160 s674 -5491 121 1061 s575 -3808 261 1111 s625 -4658 261 1161 s675 -5508 261 1062 s576 -3825 121 1112 s626 -4675 121 1162 s676 -5525 121 1063 s577 -3842 261 1113 s627 -4692 261 1163 s677 -5542 261 1064 s578 -3859 121 1114 s628 -4709 121 1164 s678 -5559 121 1065 s579 -3876 261 1115 s629 -4726 261 1165 s679 -5576 261 1066 s580 -3893 121 1116 s630 -4743 121 1166 s680 -5593 121 1067 s581 -3910 261 1117 s631 -4760 261 1167 s681 -5610 261 1068 s582 -3927 121 1118 s632 -4777 121 1168 s682 -5627 121 1069 s583 -3944 261 1119 s633 -4794 261 1169 s683 -5644 261 1070 s584 -3961 121 1120 s634 -4811 121 1170 s684 -5661 121 1071 s585 -3978 261 1121 s635 -4828 261 1171 s685 -5678 261 1072 s586 -3995 121 1122 s636 -4845 121 1172 s686 -5695 121 1073 s587 -4012 261 1123 s637 -4862 261 1173 s687 -5712 261 1074 s588 -4029 121 1124 s638 -4879 121 1174 s688 -5729 121 1075 s589 -4046 261 1125 s639 -4896 261 1175 s689 -5746 261 1076 s590 -4063 121 1126 s640 -4913 121 1176 s690 -5763 121 1077 s591 -4080 261 1127 s641 -4930 261 1177 s691 -5780 261 1078 s592 -4097 121 1128 s642 -4947 121 1178 s692 -5797 121 1079 s593 -4114 261 1129 s643 -4964 261 1179 s693 -5814 261 1080 s594 -4131 121 1130 s644 -4981 121 1180 s694 -5831 121 1081 s595 -4148 261 1131 s645 -4998 261 1181 s695 -5848 261 1082 s596 -4165 121 1132 s646 -5015 121 1182 s696 -5865 121 1083 s597 -4182 261 1133 s647 -5032 261 1183 s697 -5882 261 1084 s598 -4199 121 1134 s648 -5049 121 1184 s698 -5899 121 1085 s599 -4216 261 1135 s649 -5066 261 1185 s699 -5916 261 1086 s600 -4233 121 1136 s650 -5083 121 1186 s700 -5933 121 1087 s601 -4250 261 1137 s651 -5100 261 1187 s701 -5950 261 1088 s602 -4267 121 1138 s652 -5117 121 1188 s702 -5967 121 1089 s603 -4284 261 1139 s653 -5134 261 1189 s703 -5984 261 1090 s604 -4301 121 1140 s654 -5151 121 1190 s704 -6001 121 1091 s605 -4318 261 1141 s655 -5168 261 1191 s705 -6018 261 1092 s606 -4335 121 1142 s656 -5185 121 1192 s706 -6035 121 1093 s607 -4352 261 1143 s657 -5202 261 1193 s707 -6052 261 1094 s608 -4369 121 1144 s658 -5219 121 1194 s708 -6069 121 1095 s609 -4386 261 1145 s659 -5236 261 1195 s709 -6086 261 1096 s610 -4403 121 1146 s660 -5253 121 1196 s710 -6103 121 1097 s611 -4420 261 1147 s661 -5270 261 1197 s711 -6120 261 1098 s612 -4437 121 1148 s662 -5287 121 1198 s712 -6137 121 1099 s613 -4454 261 1149 s663 -5304 261 1199 s713 -6154 261 1100 s614 -4471 121 1150 s664 -5321 121 1200 s714 -6171 121 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 56 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 1201 s715 -6188 261 1251 g465 -7157 121 1301 g365 -8007 121 1202 s716 -6205 121 1252 g463 -7174 261 1302 g363 -8024 261 1203 s717 -6222 261 1253 g461 -7191 121 1303 g361 -8041 121 1204 s718 -6239 121 1254 g459 -7208 261 1304 g359 -8058 261 1205 s719 -6256 261 1255 g457 -7225 121 1305 g357 -8075 121 1206 s720 -6273 121 1256 g455 -7242 261 1306 g355 -8092 261 1207 com1_r -6307 261 1257 g453 -7259 121 1307 g353 -8109 121 1208 com1_r -6341 261 1258 g451 -7276 261 1308 g351 -8126 261 1209 com1_r -6375 261 1259 g449 -7293 121 1309 g349 -8143 121 1210 com1_r -6409 261 1260 g447 -7310 261 1310 g347 -8160 261 1211 com1_r -6443 261 1261 g445 -7327 121 1311 g345 -8177 121 1212 g543 -6494 261 1262 g443 -7344 261 1312 g343 -8194 261 1213 g541 -6511 121 1263 g441 -7361 121 1313 g341 -8211 121 1214 g539 -6528 261 1264 g439 -7378 261 1314 g339 -8228 261 1215 g537 -6545 121 1265 g437 -7395 121 1315 g337 -8245 121 1216 g535 -6562 261 1266 g435 -7412 261 1316 g335 -8262 261 1217 g533 -6579 121 1267 g433 -7429 121 1317 g333 -8279 121 1218 g531 -6596 261 1268 g431 -7446 261 1318 g331 -8296 261 1219 g529 -6613 121 1269 g429 -7463 121 1319 g329 -8313 121 1220 g527 -6630 261 1270 g427 -7480 261 1320 g327 -8330 261 1221 g525 -6647 121 1271 g425 -7497 121 1321 g325 -8347 121 1222 g523 -6664 261 1272 g423 -7514 261 1322 g323 -8364 261 1223 g521 -6681 121 1273 g421 -7531 121 1323 g321 -8381 121 1224 g519 -6698 261 1274 g419 -7548 261 1324 g319 -8398 261 1225 g517 -6715 121 1275 g417 -7565 121 1325 g317 -8415 121 1226 g515 -6732 261 1276 g415 -7582 261 1326 g315 -8432 261 1227 g513 -6749 121 1277 g413 -7599 121 1327 g313 -8449 121 1228 g511 -6766 261 1278 g411 -7616 261 1328 g311 -8466 261 1229 g509 -6783 121 1279 g409 -7633 121 1329 g309 -8483 121 1230 g507 -6800 261 1280 g407 -7650 261 1330 g307 -8500 261 1231 g505 -6817 121 1281 g405 -7667 121 1331 g305 -8517 121 1232 g503 -6834 261 1282 g403 -7684 261 1332 g303 -8534 261 1233 g501 -6851 121 1283 g401 -7701 121 1333 g301 -8551 121 1234 g499 -6868 261 1284 g399 -7718 261 1334 g299 -8568 261 1235 g497 -6885 121 1285 g397 -7735 121 1335 g297 -8585 121 1236 g495 -6902 261 1286 g395 -7752 261 1336 g295 -8602 261 1237 g493 -6919 121 1287 g393 -7769 121 1337 g293 -8619 121 1238 g491 -6936 261 1288 g391 -7786 261 1338 g291 -8636 261 1239 g489 -6953 121 1289 g389 -7803 121 1339 g289 -8653 121 1240 g487 -6970 261 1290 g387 -7820 261 1340 g287 -8670 261 1241 g485 -6987 121 1291 g385 -7837 121 1341 g285 -8687 121 1242 g483 -7004 261 1292 g383 -7854 261 1342 g283 -8704 261 1243 g481 -7021 121 1293 g381 -7871 121 1343 g281 -8721 121 1244 g479 -7038 261 1294 g379 -7888 261 1344 g279 -8738 261 1245 g477 -7055 121 1295 g377 -7905 121 1345 g277 -8755 121 1246 g475 -7072 261 1296 g375 -7922 261 1346 g275 -8772 261 1247 g473 -7089 121 1297 g373 -7939 121 1347 g273 -8789 121 1248 g471 -7106 261 1298 g371 -7956 261 1348 g271 -8806 261 1249 g469 -7123 121 1299 g369 -7973 121 1349 g269 -8823 121 1250 g467 -7140 261 1300 g367 -7990 261 1350 g267 -8840 261 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 57 of 60 pad no. designation cx cy pad no. designation cx cy pad no. designation cx cy 1351 g265 -8857 121 1401 g165 -9707 121 1451 g65 -10557 121 1352 g263 -8874 261 1402 g163 -9724 261 1452 g63 -10574 261 1353 g261 -8891 121 1403 g161 -9741 121 1453 g61 -10591 121 1354 g259 -8908 261 1404 g159 -9758 261 1454 g59 -10608 261 1355 g257 -8925 121 1405 g157 -9775 121 1455 g57 -10625 121 1356 g255 -8942 261 1406 g155 -9792 261 1456 g55 -10642 261 1357 g253 -8959 121 1407 g153 -9809 121 1457 g53 -10659 121 1358 g251 -8976 261 1408 g151 -9826 261 1458 g51 -10676 261 1359 g249 -8993 121 1409 g149 -9843 121 1459 g49 -10693 121 1360 g247 -9010 261 1410 g147 -9860 261 1460 g47 -10710 261 1361 g245 -9027 121 1411 g145 -9877 121 1461 g45 -10727 121 1362 g243 -9044 261 1412 g143 -9894 261 1462 g43 -10744 261 1363 g241 -9061 121 1413 g141 -9911 121 1463 g41 -10761 121 1364 g239 -9078 261 1414 g139 -9928 261 1464 g39 -10778 261 1365 g237 -9095 121 1415 g137 -9945 121 1465 g37 -10795 121 1366 g235 -9112 261 1416 g135 -9962 261 1466 g35 -10812 261 1367 g233 -9129 121 1417 g133 -9979 121 1467 g33 -10829 121 1368 g231 -9146 261 1418 g131 -9996 261 1468 g31 -10846 261 1369 g229 -9163 121 1419 g129 -10013 121 1469 g29 -10863 121 1370 g227 -9180 261 1420 g127 -10030 261 1470 g27 -10880 261 1371 g225 -9197 121 1421 g125 -10047 121 1471 g25 -10897 121 1372 g223 -9214 261 1422 g123 -10064 261 1472 g23 -10914 261 1373 g221 -9231 121 1423 g121 -10081 121 1473 g21 -10931 121 1374 g219 -9248 261 1424 g119 -10098 261 1474 g19 -10948 261 1375 g217 -9265 121 1425 g117 -10115 121 1475 g17 -10965 121 1376 g215 -9282 261 1426 g115 -10132 261 1476 g15 -10982 261 1377 g213 -9299 121 1427 g113 -10149 121 1477 g13 -10999 121 1378 g211 -9316 261 1428 g111 -10166 261 1478 g11 -11016 261 1379 g209 -9333 121 1429 g109 -10183 121 1479 g9 -11033 121 1380 g207 -9350 261 1430 g107 -10200 261 1480 g7 -11050 261 1381 g205 -9367 121 1431 g105 -10217 121 1481 g5 -11067 121 1382 g203 -9384 261 1432 g103 -10234 261 1482 g3 -11084 261 1383 g201 -9401 121 1433 g101 -10251 121 1483 g1 -11101 121 1384 g199 -9418 261 1434 g99 -10268 261 1484 dum -11135 261 1385 g197 -9435 121 1435 g97 -10285 121 1386 g195 -9452 261 1436 g95 -10302 261 1387 g193 -9469 121 1437 g93 -10319 121 1388 g191 -9486 261 1438 g91 -10336 261 1389 g189 -9503 121 1439 g89 -10353 121 1390 g187 -9520 261 1440 g87 -10370 261 1391 g185 -9537 121 1441 g85 -10387 121 1392 g183 -9554 261 1442 g83 -10404 261 1393 g181 -9571 121 1443 g81 -10421 121 1394 g179 -9588 261 1444 g79 -10438 261 1395 g177 -9605 121 1445 g77 -10455 121 1396 g175 -9622 261 1446 g75 -10472 261 1397 g173 -9639 121 1447 g73 -10489 121 1398 g171 -9656 261 1448 g71 -10506 261 1399 g169 -9673 121 1449 g69 -10523 121 1400 g167 -9690 261 1450 g67 -10540 261 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 58 of 60 16. bump mask information a a a a a a5 a5 a5 a5 a a a a5 a5 a5 a a a a5 a5 a5 a5 aa a a a a5 a5 a5 a a a a a5 a5 a5 a a a a a5 a5 a5 a a a a a5 a5 a5 a a a a a5 a5 a5 a a a a a5 a5 a5 a a a a a5 a5 a5 a a a5 a a a a5 a5 a5 a a a a a5 a5 a5 a a a5 w a6 a2 a3 a2 b3 b4 a6 a4 a1 a1 a4 b1 b2 b b2 b b2 b b2 b b2 b b2 b b2 b b2 b2 b b2 b b2 b b2 b b2 b b2 b b2 b b2 l b5 a4 a1 a6 a2 a3 a2 b3 b4 a6 105 105 15 25 15 25 25 15 15 25 25 25 105 105 15 25 15 25 25 15 15 25 25 25 left side right side alignment mark dimension unit:um (-11091um, -263.5um) (-11091um, 263.5um) symbol dimensions(um) symbol dimensions (um) symbol dimensions (um) a 17 b 30 w 732(max) a1 59 b1 57 l 22405(max) a2 110 b2 80 a3 30 b3 262 a4 105 b4 120 a5 34 b5 50 a6 50 *remark: chip dimens ion include scribe line http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 59 of 60 17. color filter arrangement the stripe color filter arrangement is shown below: r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b g2 g4 g6 g270 g272 g540 g542 g544 g1 g3 g5 g269 g271 g539 g541 g543 s720 s719 s718 s3 s2 s1 http://
single chip for 480rgbx272 tft panel 720x544 driver with timing controller ILI6480G page 60 of 60 18. revision history version no. date page description 0.00 2009/01/22 all new create 0.01 2009/01/22 p59 correct the chip length from 22405um to 22387um 0.02 2009/02/05 p4 p35 p43 p60 modify application circuit modify charge-pump circuit connection & component list modify electronic characteristic ? vcoml condition modify a1 and w dimension size 0.03 2009/02/17 p43 add vint 1 in dc characteristics 0.04 2009/03/03 p38 p44 p59 p33 modify gamma voltages add tcwl and tcwh specification add color filter arrangement modify power off sequence. http://

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